flash: Analog Devices ADuCM360 support
A target config and a simple flash driver for the ADuCM360 microcontroller. The EEPROM of the chip may be erased and programmed. Change-Id: Ic2bc2f91ec5b6f72e3976dbe18071f461fe503b8 Signed-off-by: Ivan Buliev <i.buliev@mikrosistemi.com> Reviewed-on: http://openocd.zylin.com/2787 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
This commit is contained in:
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288a1f453d
commit
03f46e3688
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@ -9,6 +9,7 @@ libocdflashnor_la_SOURCES = \
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NOR_DRIVERS = \
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aduc702x.c \
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aducm360.c \
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at91sam4.c \
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at91sam4l.c \
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at91samd.c \
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@ -0,0 +1,580 @@
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/***************************************************************************
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* Copyright (C) 2015 by Ivan Buliev *
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* i.buliev@mikrosistemi.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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***************************************************************************/
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/***************************************************************************
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* This version for ADuCM360 is largely based on the following flash *
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* drivers: *
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* - aduc702x.c *
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* Copyright (C) 2008 by Kevin McGuire *
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* Copyright (C) 2008 by Marcel Wijlaars *
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* Copyright (C) 2009 by Michael Ashton *
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* and *
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* - stm32f1x.c *
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2011 by Andreas Fritiofson *
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* andreas.fritiofson@gmail.com *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include <helper/binarybuffer.h>
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#include <helper/time_support.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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static int aducm360_build_sector_list(struct flash_bank *bank);
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static int aducm360_check_flash_completion(struct target *target, unsigned int timeout_ms);
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static int aducm360_set_write_enable(struct target *target, int enable);
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#define ADUCM360_FLASH_BASE 0x40002800
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#define ADUCM360_FLASH_FEESTA 0x0000
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#define ADUCM360_FLASH_FEECON0 0x0004
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#define ADUCM360_FLASH_FEECMD 0x0008
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#define ADUCM360_FLASH_FEEADR0L 0x0010
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#define ADUCM360_FLASH_FEEADR0H 0x0014
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#define ADUCM360_FLASH_FEEADR1L 0x0018
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#define ADUCM360_FLASH_FEEADR1H 0x001C
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#define ADUCM360_FLASH_FEEKEY 0x0020
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#define ADUCM360_FLASH_FEEPROL 0x0028
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#define ADUCM360_FLASH_FEEPROH 0x002C
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#define ADUCM360_FLASH_FEESIGL 0x0030
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#define ADUCM360_FLASH_FEESIGH 0x0034
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#define ADUCM360_FLASH_FEECON1 0x0038
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#define ADUCM360_FLASH_FEEADRAL 0x0048
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#define ADUCM360_FLASH_FEEADRAH 0x004C
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#define ADUCM360_FLASH_FEEAEN0 0x0078
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#define ADUCM360_FLASH_FEEAEN1 0x007C
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#define ADUCM360_FLASH_FEEAEN2 0x0080
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/* flash bank aducm360 0 0 0 0 <target#> */
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FLASH_BANK_COMMAND_HANDLER(aducm360_flash_bank_command)
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{
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bank->base = 0x00000000;
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bank->size = 0x00020000;
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aducm360_build_sector_list(bank);
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return ERROR_OK;
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}
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#define FLASH_SECTOR_SIZE 512
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/* ----------------------------------------------------------------------- */
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static int aducm360_build_sector_list(struct flash_bank *bank)
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{
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int i = 0;
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uint32_t offset = 0;
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/* sector size is 512 */
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bank->num_sectors = bank->size / FLASH_SECTOR_SIZE;
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bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
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for (i = 0; i < bank->num_sectors; ++i) {
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bank->sectors[i].offset = offset;
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bank->sectors[i].size = FLASH_SECTOR_SIZE;
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offset += bank->sectors[i].size;
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = 0;
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}
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return ERROR_OK;
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}
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/* ----------------------------------------------------------------------- */
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static int aducm360_protect_check(struct flash_bank *bank)
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{
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LOG_WARNING("aducm360_protect_check not implemented.");
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return ERROR_OK;
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}
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/* ----------------------------------------------------------------------- */
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static int aducm360_mass_erase(struct target *target)
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{
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uint32_t value;
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int res = ERROR_OK;
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/* Clear any old status */
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target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
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/* Enable the writing to the flash*/
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aducm360_set_write_enable(target, 1);
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/* Unlock for writing */
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F456);
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F123);
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/* Issue the 'MASSERASE' command */
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEECMD, 0x00000003);
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/* Check the result */
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res = aducm360_check_flash_completion(target, 3500);
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if (res != ERROR_OK) {
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LOG_ERROR("mass erase failed.");
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aducm360_set_write_enable(target, 0);
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res = ERROR_FLASH_OPERATION_FAILED;
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}
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return res;
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}
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/* ----------------------------------------------------------------------- */
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static int aducm360_page_erase(struct target *target, uint32_t padd)
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{
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uint32_t value;
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int res = ERROR_OK;
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/* Clear any old status */
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target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
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/* Enable the writing to the flash*/
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aducm360_set_write_enable(target, 1);
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/* Unlock for writing */
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F456);
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F123);
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/* Write the sector address */
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEADR0L, padd & 0xFFFF);
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEADR0H, (padd>>16) & 0xFFFF);
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/* Issue the 'ERASEPAGE' command */
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target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEECMD, 0x00000001);
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/* Check the result */
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res = aducm360_check_flash_completion(target, 50);
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if (res != ERROR_OK) {
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LOG_ERROR("page erase failed at 0x%08" PRIx32, padd);
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aducm360_set_write_enable(target, 0);
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res = ERROR_FLASH_OPERATION_FAILED;
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}
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return res;
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}
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/* ----------------------------------------------------------------------- */
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static int aducm360_erase(struct flash_bank *bank, int first, int last)
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{
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int res = ERROR_OK;
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int i;
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int count;
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struct target *target = bank->target;
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uint32_t padd;
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if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
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res = aducm360_mass_erase(target);
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} else {
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count = last - first + 1;
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for (i = 0; i < count; ++i) {
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padd = bank->base + ((first+i)*FLASH_SECTOR_SIZE);
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res = aducm360_page_erase(target, padd);
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if (res != ERROR_OK)
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break;
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}
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}
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return res;
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}
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/* ----------------------------------------------------------------------- */
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static int aducm360_protect(struct flash_bank *bank, int set, int first, int last)
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{
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LOG_ERROR("aducm360_protect not implemented.");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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/* ----------------------------------------------------------------------- */
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static int aducm360_write_block_sync(
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struct flash_bank *bank,
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const uint8_t *buffer,
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uint32_t offset,
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uint32_t count)
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{
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struct target *target = bank->target;
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uint32_t target_buffer_size = 8192;
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struct working_area *helper;
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struct working_area *target_buffer;
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uint32_t address = bank->base + offset;
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struct reg_param reg_params[8];
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int retval = ERROR_OK;
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uint32_t entry_point = 0, exit_point = 0;
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uint32_t res;
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struct armv7m_algorithm armv7m_algo;
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static const uint32_t aducm360_flash_write_code[] = {
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/* helper.code */
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0x88AF4D10, 0x0704F047, 0x682F80AF, 0x600E6806,
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0xF017882F, 0xF43F0F08, 0xF851AFFB, 0x42B77B04,
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0x800DF040, 0x0004F100, 0xF47F3A04, 0x686FAFEF,
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0x0704F027, 0xF04F80AF, 0xF0000400, 0xF04FB802,
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0xBE000480, 0x40002800, 0x00015000, 0x20000000,
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0x00013000
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};
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LOG_DEBUG("'aducm360_write_block_sync' requested, dst:0x%08" PRIx32 ", count:0x%08" PRIx32 "bytes.",
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address, count);
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/* ----- Check the destination area for a Long Word alignment ----- */
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if (((count%4) != 0) || ((offset%4) != 0)) {
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LOG_ERROR("write block must be multiple of four bytes in offset & length");
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return ERROR_FAIL;
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}
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/* ----- Allocate space in the target's RAM for the helper code ----- */
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if (target_alloc_working_area(target, sizeof(aducm360_flash_write_code),
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&helper) != ERROR_OK) {
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LOG_WARNING("no working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* ----- Upload the helper code to the space in the target's RAM ----- */
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uint8_t code[sizeof(aducm360_flash_write_code)];
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target_buffer_set_u32_array(target, code, ARRAY_SIZE(aducm360_flash_write_code),
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aducm360_flash_write_code);
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retval = target_write_buffer(target, helper->address, sizeof(code), code);
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if (retval != ERROR_OK)
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return retval;
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entry_point = helper->address;
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/* ----- Allocate space in the target's RAM for the user application's object code ----- */
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while (target_alloc_working_area_try(target, target_buffer_size, &target_buffer) != ERROR_OK) {
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LOG_WARNING("couldn't allocate a buffer space of 0x%08" PRIx32 "bytes in the target's SRAM.",
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target_buffer_size);
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target_buffer_size /= 2;
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if (target_buffer_size <= 256) { /* No room available */
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LOG_WARNING("no large enough working area available, can't do block memory writes");
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target_free_working_area(target, helper);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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}
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/* ----- Prepare the target for the helper ----- */
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armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
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armv7m_algo.core_mode = ARM_MODE_THREAD;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /*SRC */
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /*DST */
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /*COUNT */
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init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /*not used */
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init_reg_param(®_params[4], "r4", 32, PARAM_IN); /*RESULT */
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/* ===== Execute the Main Programming Loop! ===== */
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while (count > 0) {
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uint32_t thisrun_count = (count > target_buffer_size) ? target_buffer_size : count;
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/* ----- Upload the chunk ----- */
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retval = target_write_buffer(target, target_buffer->address, thisrun_count, buffer);
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if (retval != ERROR_OK)
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break;
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/* Set the arguments for the helper */
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buf_set_u32(reg_params[0].value, 0, 32, target_buffer->address); /*SRC */
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buf_set_u32(reg_params[1].value, 0, 32, address); /*DST */
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buf_set_u32(reg_params[2].value, 0, 32, thisrun_count); /*COUNT */
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buf_set_u32(reg_params[3].value, 0, 32, 0); /*NOT USED*/
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retval = target_run_algorithm(target, 0, NULL, 5,
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reg_params, entry_point, exit_point, 10000, &armv7m_algo);
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if (retval != ERROR_OK) {
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LOG_ERROR("error executing aducm360 flash write algorithm");
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break;
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}
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res = buf_get_u32(reg_params[4].value, 0, 32);
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if (res) {
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LOG_ERROR("aducm360 fast sync algorithm reports an error (%02X)", res);
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retval = ERROR_FAIL;
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break;
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}
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buffer += thisrun_count;
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address += thisrun_count;
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count -= thisrun_count;
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}
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target_free_working_area(target, target_buffer);
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target_free_working_area(target, helper);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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destroy_reg_param(®_params[3]);
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destroy_reg_param(®_params[4]);
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return retval;
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}
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/* ----------------------------------------------------------------------- */
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static int aducm360_write_block_async(
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struct flash_bank *bank,
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const uint8_t *buffer,
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uint32_t offset,
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uint32_t count)
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{
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struct target *target = bank->target;
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uint32_t target_buffer_size = 1024;
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struct working_area *helper;
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struct working_area *target_buffer;
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uint32_t address = bank->base + offset;
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struct reg_param reg_params[9];
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int retval = ERROR_OK;
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uint32_t entry_point = 0, exit_point = 0;
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uint32_t res;
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uint32_t wcount;
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struct armv7m_algorithm armv7m_algo;
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static const uint32_t aducm360_flash_write_code[] = {
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/* helper.code */
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0x4050F8DF, 0xF04588A5, 0x80A50504, 0x8000F8D0,
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0x0F00F1B8, 0x8016F000, 0x45476847, 0xAFF6F43F,
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0x6B04F857, 0x6B04F842, 0xF0158825, 0xF43F0F08,
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0x428FAFFB, 0xF100BF28, 0x60470708, 0xB10B3B01,
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0xBFE4F7FF, 0xF02588A5, 0x80A50504, 0x0900F04F,
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0xBE00BF00, 0x40002800, 0x20000000, 0x20000100,
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0x00013000
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};
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LOG_DEBUG("'aducm360_write_block_async' requested, dst:0x%08" PRIx32 ", count:0x%08" PRIx32 "bytes.",
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address, count);
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/* ----- Check the destination area for a Long Word alignment ----- */
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if (((count%4) != 0) || ((offset%4) != 0)) {
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LOG_ERROR("write block must be multiple of four bytes in offset & length");
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return ERROR_FAIL;
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}
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wcount = count/4;
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/* ----- Allocate space in the target's RAM for the helper code ----- */
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if (target_alloc_working_area(target, sizeof(aducm360_flash_write_code),
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&helper) != ERROR_OK) {
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LOG_WARNING("no working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* ----- Upload the helper code to the space in the target's RAM ----- */
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uint8_t code[sizeof(aducm360_flash_write_code)];
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target_buffer_set_u32_array(target, code, ARRAY_SIZE(aducm360_flash_write_code),
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aducm360_flash_write_code);
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retval = target_write_buffer(target, helper->address, sizeof(code), code);
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if (retval != ERROR_OK)
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return retval;
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entry_point = helper->address;
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/* ----- Allocate space in the target's RAM for the user application's object code ----- */
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while (target_alloc_working_area_try(target, target_buffer_size, &target_buffer) != ERROR_OK) {
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LOG_WARNING("couldn't allocate a buffer space of 0x%08" PRIx32 "bytes in the target's SRAM.",
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target_buffer_size);
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target_buffer_size /= 2;
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if (target_buffer_size <= 256) { /* No room available */
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LOG_WARNING("no large enough working area available, can't do block memory writes");
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target_free_working_area(target, helper);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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}
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/* ----- Prepare the target for the helper ----- */
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armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
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armv7m_algo.core_mode = ARM_MODE_THREAD;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /*SRCBEG */
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /*SRCEND */
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /*DST */
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init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /*COUNT (LWs)*/
|
||||
init_reg_param(®_params[4], "r9", 32, PARAM_IN); /*RESULT */
|
||||
|
||||
buf_set_u32(reg_params[0].value, 0, 32, target_buffer->address);
|
||||
buf_set_u32(reg_params[1].value, 0, 32, target_buffer->address + target_buffer->size);
|
||||
buf_set_u32(reg_params[2].value, 0, 32, address);
|
||||
buf_set_u32(reg_params[3].value, 0, 32, wcount);
|
||||
|
||||
retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
|
||||
0, NULL,
|
||||
5, reg_params,
|
||||
target_buffer->address, target_buffer->size,
|
||||
entry_point, exit_point,
|
||||
&armv7m_algo);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("error executing aducm360 flash write algorithm");
|
||||
} else {
|
||||
res = buf_get_u32(reg_params[4].value, 0, 32); /*RESULT*/
|
||||
if (res) {
|
||||
LOG_ERROR("aducm360 fast async algorithm reports an error (%02X)", res);
|
||||
retval = ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
target_free_working_area(target, target_buffer);
|
||||
target_free_working_area(target, helper);
|
||||
|
||||
destroy_reg_param(®_params[0]);
|
||||
destroy_reg_param(®_params[1]);
|
||||
destroy_reg_param(®_params[2]);
|
||||
destroy_reg_param(®_params[3]);
|
||||
destroy_reg_param(®_params[4]);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* If this fn returns ERROR_TARGET_RESOURCE_NOT_AVAILABLE, then the caller can fall
|
||||
* back to another mechanism that does not require onboard RAM
|
||||
*
|
||||
* Caller should not check for other return values specifically
|
||||
*/
|
||||
static int aducm360_write_block(struct flash_bank *bank,
|
||||
const uint8_t *buffer,
|
||||
uint32_t offset,
|
||||
uint32_t count)
|
||||
{
|
||||
int choice = 0;
|
||||
|
||||
switch (choice) {
|
||||
case 0:
|
||||
return aducm360_write_block_sync(bank, buffer, offset, count);
|
||||
break;
|
||||
case 1:
|
||||
return aducm360_write_block_async(bank, buffer, offset, count);
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("aducm360_write_block was cancelled (no writing method was chosen)!");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define FEESTA_WRDONE 0x00000008
|
||||
|
||||
static int aducm360_write_modified(struct flash_bank *bank,
|
||||
const uint8_t *buffer,
|
||||
uint32_t offset,
|
||||
uint32_t count)
|
||||
{
|
||||
uint32_t value;
|
||||
int res = ERROR_OK;
|
||||
uint32_t i, j, a, d;
|
||||
struct target *target = bank->target;
|
||||
|
||||
LOG_DEBUG("performing slow write (offset=0x%08" PRIx32 ", count=0x%08" PRIx32 ")...",
|
||||
offset, count);
|
||||
|
||||
/* Enable the writing to the flash */
|
||||
aducm360_set_write_enable(target, 1);
|
||||
|
||||
/* Clear any old status */
|
||||
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
|
||||
|
||||
for (i = 0; i < count; i += 4) {
|
||||
a = offset+i;
|
||||
for (j = 0; i < 4; i += 1)
|
||||
*((uint8_t *)(&d) + j) = buffer[i+j];
|
||||
target_write_u32(target, a, d);
|
||||
do {
|
||||
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
|
||||
} while (!(value & FEESTA_WRDONE));
|
||||
}
|
||||
aducm360_set_write_enable(target, 0);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
static int aducm360_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
|
||||
{
|
||||
int retval;
|
||||
|
||||
/* try using a block write */
|
||||
retval = aducm360_write_block(bank, buffer, offset, count);
|
||||
if (retval != ERROR_OK) {
|
||||
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
|
||||
/* if block write failed (no sufficient working area),
|
||||
* use normal (slow) JTAG method */
|
||||
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
||||
|
||||
retval = aducm360_write_modified(bank, buffer, offset, count);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("slow write failed");
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
}
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
static int aducm360_probe(struct flash_bank *bank)
|
||||
{
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* sets FEECON0 bit 2
|
||||
* enable = 1 enables writes & erases, 0 disables them */
|
||||
static int aducm360_set_write_enable(struct target *target, int enable)
|
||||
{
|
||||
/* don't bother to preserve int enable bit here */
|
||||
uint32_t value;
|
||||
|
||||
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEECON0, &value);
|
||||
if (enable)
|
||||
value |= 0x00000004;
|
||||
else
|
||||
value &= ~0x00000004;
|
||||
target_write_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEECON0, value);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* wait up to timeout_ms for controller to not be busy,
|
||||
* then check whether the command passed or failed.
|
||||
*
|
||||
* this function sleeps 1ms between checks (after the first one),
|
||||
* so in some cases may slow things down without a usleep after the first read */
|
||||
static int aducm360_check_flash_completion(struct target *target, unsigned int timeout_ms)
|
||||
{
|
||||
uint32_t v = 1;
|
||||
|
||||
long long endtime = timeval_ms() + timeout_ms;
|
||||
while (1) {
|
||||
target_read_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEESTA, &v);
|
||||
if ((v & 0x00000001) == 0)
|
||||
break;
|
||||
alive_sleep(1);
|
||||
if (timeval_ms() >= endtime)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!(v & 0x00000004)) /* b2 */
|
||||
return ERROR_FAIL;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
struct flash_driver aducm360_flash = {
|
||||
.name = "aducm360",
|
||||
.flash_bank_command = aducm360_flash_bank_command,
|
||||
.erase = aducm360_erase,
|
||||
.protect = aducm360_protect,
|
||||
.write = aducm360_write,
|
||||
.read = default_flash_read,
|
||||
.probe = aducm360_probe,
|
||||
.auto_probe = aducm360_probe,
|
||||
.erase_check = default_flash_blank_check,
|
||||
.protect_check = aducm360_protect_check,
|
||||
};
|
|
@ -35,6 +35,7 @@ extern struct flash_driver at91sam7_flash;
|
|||
extern struct flash_driver str7x_flash;
|
||||
extern struct flash_driver str9x_flash;
|
||||
extern struct flash_driver aduc702x_flash;
|
||||
extern struct flash_driver aducm360_flash;
|
||||
extern struct flash_driver stellaris_flash;
|
||||
extern struct flash_driver str9xpec_flash;
|
||||
extern struct flash_driver stm32f1x_flash;
|
||||
|
@ -79,6 +80,7 @@ static struct flash_driver *flash_drivers[] = {
|
|||
&str7x_flash,
|
||||
&str9x_flash,
|
||||
&aduc702x_flash,
|
||||
&aducm360_flash,
|
||||
&stellaris_flash,
|
||||
&str9xpec_flash,
|
||||
&stm32f1x_flash,
|
||||
|
|
|
@ -0,0 +1,55 @@
|
|||
#
|
||||
# This file was created using as references the stm32f1x.cfg and aduc702x.cfg
|
||||
#
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
# Chip name
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME aducm360
|
||||
}
|
||||
|
||||
# Endianess
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
# Work-area is a space in RAM used for flash programming
|
||||
# Eventually, the whole SRAM of ADuCM360 will be used (8kB)
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x2000
|
||||
}
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x2ba01477
|
||||
}
|
||||
|
||||
swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# SWD/JTAG speed
|
||||
adapter_khz 1000
|
||||
|
||||
##
|
||||
## Target configuration
|
||||
##
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# allocate the working area
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
# flash size will be probed
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
|
||||
|
||||
adapter_nsrst_delay 100
|
||||
|
||||
cortex_m reset_config sysresetreq
|
Loading…
Reference in New Issue