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ARM: rename some generic routines 

Rename some (mostly) generic ARM functions:

    armv4_5_arch_state()       --> arm_arch_state()
    armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list()
    armv4_5_init_arch_info()   --> arm_init_arch_info()

Cores using the microcontroller profile may want a different
arch_state() routine though.

(Also fix strange indentation in arm_arch_state: use tabs only!
And update a call to it, removing assignment-in-conditional.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-12-07 14:54:13 -08:00
parent a4a2808c2a
commit 0529c14bfe
15 changed files with 34 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/target/arm11.c
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@ -373,7 +373,7 @@ static int arm11_arch_state(struct target *target)
struct arm11_common *arm11 = target_to_arm11(target);
int retval;
retval = armv4_5_arch_state(target);
retval = arm_arch_state(target);
/* REVISIT also display ARM11-specific MMU and cache status ... */
@ -1150,7 +1150,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
if (!arm11)
return ERROR_FAIL;
armv4_5_init_arch_info(target, &arm11->arm);
arm_init_arch_info(target, &arm11->arm);
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
@ -1387,7 +1387,7 @@ struct target_type arm11_target = {
.deassert_reset = arm11_deassert_reset,
.soft_reset_halt = arm11_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm11_read_memory,
.write_memory = arm11_write_memory,

2
src/target/arm720t.c
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@ -557,7 +557,7 @@ struct target_type arm720t_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm720t_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm720t_read_memory,
.write_memory = arm7_9_write_memory,

3
src/target/arm7_9_common.c
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@ -2885,7 +2885,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
armv4_5->write_core_reg = arm7_9_write_core_reg;
armv4_5->full_context = arm7_9_full_context;
if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
retval = arm_init_arch_info(target, armv4_5);
if (retval != ERROR_OK)
return retval;
return target_register_timer_callback(arm7_9_handle_target_request,

4
src/target/arm7tdmi.c
View File

@ -720,7 +720,7 @@ struct target_type arm7tdmi_target =
.name = "arm7tdmi",
.poll = arm7_9_poll,
.arch_state = armv4_5_arch_state,
.arch_state = arm_arch_state,
.target_request_data = arm7_9_target_request_data,
@ -732,7 +732,7 @@ struct target_type arm7tdmi_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,

2
src/target/arm920t.c
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@ -1453,7 +1453,7 @@ struct target_type arm920t_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm920t_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm920t_read_memory,
.write_memory = arm920t_write_memory,

2
src/target/arm926ejs.c
View File

@ -801,7 +801,7 @@ struct target_type arm926ejs_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm926ejs_write_memory,

4
src/target/arm966e.c
View File

@ -252,7 +252,7 @@ struct target_type arm966e_target =
.name = "arm966e",
.poll = arm7_9_poll,
.arch_state = armv4_5_arch_state,
.arch_state = arm_arch_state,
.target_request_data = arm7_9_target_request_data,
@ -264,7 +264,7 @@ struct target_type arm966e_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,

4
src/target/arm9tdmi.c
View File

@ -937,7 +937,7 @@ struct target_type arm9tdmi_target =
.name = "arm9tdmi",
.poll = arm7_9_poll,
.arch_state = armv4_5_arch_state,
.arch_state = arm_arch_state,
.target_request_data = arm7_9_target_request_data,
@ -949,7 +949,7 @@ struct target_type arm9tdmi_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,

15
src/target/armv4_5.c
View File

@ -581,7 +581,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
return cache;
}
int armv4_5_arch_state(struct target *target)
int arm_arch_state(struct target *target)
{
struct arm *armv4_5 = target_to_arm(target);
@ -593,11 +593,11 @@ int armv4_5_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value,
0, 32),
armv4_5->is_semihosting ? ", semihosting" : "");
@ -972,7 +972,8 @@ const struct command_registration arm_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size)
{
struct arm *armv4_5 = target_to_arm(target);
int i;
@ -1419,7 +1420,7 @@ static int arm_default_mcr(struct target *target, int cpnum,
return ERROR_FAIL;
}
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
int arm_init_arch_info(struct target *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
armv4_5->target = target;

6
src/target/armv4_5.h
View File

@ -187,13 +187,13 @@ struct arm_reg
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
int armv4_5_arch_state(struct target *target);
int armv4_5_get_gdb_reg_list(struct target *target,
int arm_arch_state(struct target *target);
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size);
extern const struct command_registration arm_command_handlers[];
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
int arm_init_arch_info(struct target *target, struct arm *arm);
int armv4_5_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,

2
src/target/armv7a.c
View File

@ -100,7 +100,7 @@ int armv7a_arch_state(struct target *target)
return ERROR_INVALID_ARGUMENTS;
}
armv4_5_arch_state(target);
arm_arch_state(target);
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
state[armv7a->armv4_5_mmu.mmu_enabled],

4
src/target/cortex_a8.c
View File

@ -1603,7 +1603,7 @@ static int cortex_a8_init_arch_info(struct target *target,
// arm7_9->handle_target_request = cortex_a8_handle_target_request;
/* REVISIT v7a setup should be in a v7a-specific routine */
armv4_5_init_arch_info(target, armv4_5);
arm_init_arch_info(target, armv4_5);
armv7a->common_magic = ARMV7_COMMON_MAGIC;
target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
@ -1686,7 +1686,7 @@ struct target_type cortexa8_target = {
.deassert_reset = cortex_a8_deassert_reset,
.soft_reset_halt = NULL,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = cortex_a8_read_memory,
.write_memory = cortex_a8_write_memory,

2
src/target/fa526.c
View File

@ -370,7 +370,7 @@ struct target_type fa526_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm920t_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm920t_read_memory,
.write_memory = arm920t_write_memory,

6
src/target/feroceon.c
View File

@ -694,7 +694,7 @@ struct target_type feroceon_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm926ejs_write_memory,
@ -721,7 +721,7 @@ struct target_type dragonite_target =
.name = "dragonite",
.poll = arm7_9_poll,
.arch_state = armv4_5_arch_state,
.arch_state = arm_arch_state,
.target_request_data = arm7_9_target_request_data,
@ -733,7 +733,7 @@ struct target_type dragonite_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,

4
src/target/xscale.c
View File

@ -2993,7 +2993,7 @@ static int xscale_init_arch_info(struct target *target,
armv4_5->write_core_reg = xscale_write_core_reg;
armv4_5->full_context = xscale_full_context;
armv4_5_init_arch_info(target, armv4_5);
arm_init_arch_info(target, armv4_5);
xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
@ -3722,7 +3722,7 @@ struct target_type xscale_target =
.deassert_reset = xscale_deassert_reset,
.soft_reset_halt = NULL,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = xscale_read_memory,
.read_phys_memory = xscale_read_phys_memory,