target/arc: Introduce L1I,L1D,L2 caches support
With this commit we introduce L1 and L2 cache flush and invalidate operations which are necessary for getting/setting actual data during memory r/w operations. We introduce L2 cache support, which is not presented on currently support EMSK board. But L2 is presented on HSDK board, which soon will be introduced. Change-Id: I2fda505a47ecb8833cc9f5ffe24f6a4e22ab6eb0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5688 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Evgeniy Didin
Antonio Borneo
parent
2e6904eef5
commit
057aed11a2
214
src/target/arc.c
214
src/target/arc.c
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@ -86,6 +86,26 @@ struct reg *arc_reg_get_by_name(struct reg_cache *first,
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return NULL;
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}
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/**
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* Reset internal states of caches. Must be called when entering debugging.
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*
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* @param target Target for which to reset caches states.
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*/
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int arc_reset_caches_states(struct target *target)
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{
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struct arc_common *arc = target_to_arc(target);
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LOG_DEBUG("Resetting internal variables of caches states");
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/* Reset caches states. */
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arc->dcache_flushed = false;
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arc->l2cache_flushed = false;
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arc->icache_invalidated = false;
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arc->dcache_invalidated = false;
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arc->l2cache_invalidated = false;
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return ERROR_OK;
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}
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/* Initialize arc_common structure, which passes to openocd target instance */
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static int arc_init_arch_info(struct target *target, struct arc_common *arc,
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@ -102,6 +122,15 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc,
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return ERROR_FAIL;
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}
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/* On most ARC targets there is a dcache, so we enable its flushing
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* by default. If there no dcache, there will be no error, just a slight
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* performance penalty from unnecessary JTAG operations. */
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arc->has_dcache = true;
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arc->has_icache = true;
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/* L2$ is not available in a target by default. */
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arc->has_l2cache = false;
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arc_reset_caches_states(target);
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/* Add standard GDB data types */
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INIT_LIST_HEAD(&arc->reg_data_types);
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struct arc_reg_data_type *std_types = calloc(ARRAY_SIZE(standard_gdb_types),
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@ -900,6 +929,7 @@ static int arc_debug_entry(struct target *target)
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/* TODO: reset internal indicators of caches states, otherwise D$/I$
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* will not be flushed/invalidated when required. */
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CHECK_RETVAL(arc_reset_caches_states(target));
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CHECK_RETVAL(arc_examine_debug_reason(target));
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return ERROR_OK;
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@ -1152,6 +1182,11 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
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LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i,"
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" debug_execution:%i", current, address, handle_breakpoints, debug_execution);
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/* We need to reset ARC cache variables so caches
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* would be invalidated and actual data
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* would be fetched from memory. */
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CHECK_RETVAL(arc_reset_caches_states(target));
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if (target->state != TARGET_HALTED) {
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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@ -1396,8 +1431,9 @@ static int arc_set_breakpoint(struct target *target,
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LOG_DEBUG("ERROR: setting unknown breakpoint type");
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return ERROR_FAIL;
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}
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/* core instruction cache is now invalid,
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* TODO: add cache invalidation function here (when implemented). */
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/* core instruction cache is now invalid. */
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CHECK_RETVAL(arc_cache_invalidate(target));
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return ERROR_OK;
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}
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@ -1462,8 +1498,8 @@ static int arc_unset_breakpoint(struct target *target,
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return ERROR_FAIL;
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}
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/* core instruction cache is now invalid.
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* TODO: Add cache invalidation function */
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/* core instruction cache is now invalid. */
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CHECK_RETVAL(arc_cache_invalidate(target));
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return retval;
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}
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@ -1596,6 +1632,176 @@ int arc_step(struct target *target, int current, target_addr_t address,
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}
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/* This function invalidates icache. */
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static int arc_icache_invalidate(struct target *target)
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{
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uint32_t value;
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struct arc_common *arc = target_to_arc(target);
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/* Don't waste time if already done. */
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if (!arc->has_icache || arc->icache_invalidated)
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return ERROR_OK;
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LOG_DEBUG("Invalidating I$.");
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value = IC_IVIC_INVALIDATE; /* invalidate I$ */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
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arc->icache_invalidated = true;
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return ERROR_OK;
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}
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/* This function invalidates dcache */
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static int arc_dcache_invalidate(struct target *target)
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{
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uint32_t value, dc_ctrl_value;
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struct arc_common *arc = target_to_arc(target);
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if (!arc->has_dcache || arc->dcache_invalidated)
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return ERROR_OK;
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LOG_DEBUG("Invalidating D$.");
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CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
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dc_ctrl_value = value;
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value &= ~DC_CTRL_IM;
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/* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
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value = DC_IVDC_INVALIDATE; /* invalidate D$ */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
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/* restore DC_CTRL invalidate mode */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
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arc->dcache_invalidated = true;
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return ERROR_OK;
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}
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/* This function invalidates l2 cache. */
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static int arc_l2cache_invalidate(struct target *target)
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{
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uint32_t value, slc_ctrl_value;
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struct arc_common *arc = target_to_arc(target);
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if (!arc->has_l2cache || arc->l2cache_invalidated)
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return ERROR_OK;
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LOG_DEBUG("Invalidating L2$.");
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CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
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slc_ctrl_value = value;
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value &= ~L2_CTRL_IM;
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/* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, value));
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/* invalidate L2$ */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_INV, L2_INV_IV));
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/* Wait until invalidate operation ends */
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do {
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LOG_DEBUG("Waiting for invalidation end.");
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CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
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} while (value & L2_CTRL_BS);
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/* restore L2_CTRL invalidate mode */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, slc_ctrl_value));
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arc->l2cache_invalidated = true;
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return ERROR_OK;
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}
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int arc_cache_invalidate(struct target *target)
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{
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CHECK_RETVAL(arc_icache_invalidate(target));
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CHECK_RETVAL(arc_dcache_invalidate(target));
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CHECK_RETVAL(arc_l2cache_invalidate(target));
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return ERROR_OK;
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}
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/* Flush data cache. This function is cheap to call and return quickly if D$
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* already has been flushed since target had been halted. JTAG debugger reads
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* values directly from memory, bypassing cache, so if there are unflushed
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* lines debugger will read invalid values, which will cause a lot of troubles.
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* */
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int arc_dcache_flush(struct target *target)
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{
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uint32_t value, dc_ctrl_value;
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bool has_to_set_dc_ctrl_im;
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struct arc_common *arc = target_to_arc(target);
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/* Don't waste time if already done. */
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if (!arc->has_dcache || arc->dcache_flushed)
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return ERROR_OK;
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LOG_DEBUG("Flushing D$.");
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/* Store current value of DC_CTRL */
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CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
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/* Set DC_CTRL invalidate mode to flush (if not already set) */
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has_to_set_dc_ctrl_im = (dc_ctrl_value & DC_CTRL_IM) == 0;
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if (has_to_set_dc_ctrl_im) {
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value = dc_ctrl_value | DC_CTRL_IM;
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
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}
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/* Flush D$ */
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value = DC_IVDC_INVALIDATE;
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
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/* Restore DC_CTRL invalidate mode (even of flush failed) */
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if (has_to_set_dc_ctrl_im)
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
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arc->dcache_flushed = true;
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return ERROR_OK;
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}
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/* This function flushes l2cache. */
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static int arc_l2cache_flush(struct target *target)
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{
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uint32_t value;
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struct arc_common *arc = target_to_arc(target);
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/* Don't waste time if already done. */
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if (!arc->has_l2cache || arc->l2cache_flushed)
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return ERROR_OK;
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LOG_DEBUG("Flushing L2$.");
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/* Flush L2 cache */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
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/* Wait until flush operation ends */
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do {
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LOG_DEBUG("Waiting for flushing end.");
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CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
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} while (value & L2_CTRL_BS);
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arc->l2cache_flushed = true;
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return ERROR_OK;
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}
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int arc_cache_flush(struct target *target)
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{
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CHECK_RETVAL(arc_dcache_flush(target));
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CHECK_RETVAL(arc_l2cache_flush(target));
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return ERROR_OK;
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}
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/* ARC v2 target */
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struct target_type arcv2_target = {
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@ -60,6 +60,24 @@
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/* ARC 16bits opcodes */
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#define ARC_SDBBP_16 0x7FFF /* BRK_S */
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/* Cache registers */
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#define AUX_IC_IVIC_REG 0X10
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#define IC_IVIC_INVALIDATE 0XFFFFFFFF
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#define AUX_DC_IVDC_REG 0X47
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#define DC_IVDC_INVALIDATE BIT(0)
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#define AUX_DC_CTRL_REG 0X48
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#define DC_CTRL_IM BIT(6)
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/* L2 cache registers */
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#define SLC_AUX_CACHE_CTRL 0x903
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#define L2_CTRL_IM BIT(6)
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#define L2_CTRL_BS BIT(8) /* Busy flag */
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#define SLC_AUX_CACHE_FLUSH 0x904
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#define L2_FLUSH_FL BIT(0)
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#define SLC_AUX_CACHE_INV 0x905
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#define L2_INV_IV BIT(0)
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struct arc_reg_bitfield {
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struct reg_data_type_bitfield bitfield;
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char name[REG_TYPE_MAX_NAME_LENGTH];
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@ -109,6 +127,22 @@ struct arc_common {
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struct reg_cache *core_and_aux_cache;
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struct reg_cache *bcr_cache;
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/* Cache control */
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bool has_dcache;
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bool has_icache;
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bool has_l2cache;
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/* If true, then D$ has been already flushed since core has been
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* halted. */
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bool dcache_flushed;
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/* If true, then L2 has been already flushed since core has been
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* halted. */
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bool l2cache_flushed;
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/* If true, then caches have been already flushed since core has been
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* halted. */
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bool icache_invalidated;
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bool dcache_invalidated;
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bool l2cache_invalidated;
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/* Indicate if cach was built (for deinit function) */
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bool core_aux_cache_built;
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bool bcr_cache_built;
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@ -247,4 +281,7 @@ struct reg *arc_reg_get_by_name(struct reg_cache *first,
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int arc_reg_get_field(struct target *target, const char *reg_name,
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const char *field_name, uint32_t *value_ptr);
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int arc_cache_flush(struct target *target);
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int arc_cache_invalidate(struct target *target);
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#endif /* OPENOCD_TARGET_ARC_H */
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@ -909,10 +909,60 @@ static int jim_arc_get_reg_field(Jim_Interp *interp, int argc, Jim_Obj * const *
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return JIM_OK;
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}
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COMMAND_HANDLER(arc_l1_cache_disable_auto_cmd)
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{
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bool value;
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int retval = 0;
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struct arc_common *arc = target_to_arc(get_current_target(CMD_CTX));
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retval = CALL_COMMAND_HANDLER(handle_command_parse_bool,
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&value, "target has caches enabled");
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arc->has_l2cache = value;
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arc->has_dcache = value;
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arc->has_icache = value;
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return retval;
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}
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COMMAND_HANDLER(arc_l2_cache_disable_auto_cmd)
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{
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struct arc_common *arc = target_to_arc(get_current_target(CMD_CTX));
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return CALL_COMMAND_HANDLER(handle_command_parse_bool,
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&arc->has_l2cache, "target has l2 cache enabled");
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}
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/* ----- Exported target commands ------------------------------------------ */
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const struct command_registration arc_l2_cache_group_handlers[] = {
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{
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.name = "auto",
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.handler = arc_l2_cache_disable_auto_cmd,
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.mode = COMMAND_ANY,
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.usage = "(1|0)",
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.help = "Disable or enable L2",
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},
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COMMAND_REGISTRATION_DONE
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};
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const struct command_registration arc_cache_group_handlers[] = {
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{
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.name = "auto",
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.handler = arc_l1_cache_disable_auto_cmd,
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.mode = COMMAND_ANY,
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.help = "Disable or enable L1",
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.usage = "(1|0)",
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},
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{
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.name = "l2",
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.mode = COMMAND_ANY,
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.help = "L2 cache command group",
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.usage = "",
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.chain = arc_l2_cache_group_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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static const struct command_registration arc_core_command_handlers[] = {
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{
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{
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.name = "add-reg-type-flags",
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.jim_handler = jim_arc_add_reg_type_flags,
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.mode = COMMAND_CONFIG,
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@ -967,6 +1017,13 @@ static const struct command_registration arc_core_command_handlers[] = {
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.usage = "",
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.chain = arc_jtag_command_group,
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},
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{
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.name = "cache",
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.mode = COMMAND_ANY,
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.help = "cache command group",
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.usage = "",
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.chain = arc_cache_group_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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@ -41,10 +41,18 @@ static int arc_mem_write_block32(struct target *target, uint32_t addr,
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/* Check arguments */
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assert(!(addr & 3));
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/* We need to flush the cache since it might contain dirty
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* lines, so the cache invalidation may cause data inconsistency. */
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CHECK_RETVAL(arc_cache_flush(target));
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/* No need to flush cache, because we don't read values from memory. */
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CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, addr, count,
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(uint32_t *)buf));
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/* Invalidate caches. */
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CHECK_RETVAL(arc_cache_invalidate(target));
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return ERROR_OK;
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}
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@ -64,6 +72,9 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr,
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/* Check arguments */
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assert(!(addr & 1));
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/* We will read data from memory, so we need to flush the cache. */
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CHECK_RETVAL(arc_cache_flush(target));
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/* non-word writes are less common, than 4-byte writes, so I suppose we can
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* allowe ourselves to write this in a cycle, instead of calling arc_jtag
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* with count > 1. */
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@ -97,6 +108,9 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr,
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(addr + i * sizeof(uint16_t)) & ~3u, 1, &buffer_he));
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}
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/* Invalidate caches. */
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CHECK_RETVAL(arc_cache_invalidate(target));
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return ERROR_OK;
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}
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@ -113,6 +127,9 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr,
|
|||
LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
|
||||
addr, count);
|
||||
|
||||
/* We will read data from memory, so we need to flush the cache. */
|
||||
CHECK_RETVAL(arc_cache_flush(target));
|
||||
|
||||
/* non-word writes are less common, than 4-byte writes, so I suppose we can
|
||||
* allowe ourselves to write this in a cycle, instead of calling arc_jtag
|
||||
* with count > 1. */
|
||||
|
|
@ -128,6 +145,9 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr,
|
|||
CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, (addr + i) & ~3, 1, &buffer_he));
|
||||
}
|
||||
|
||||
/* Invalidate caches. */
|
||||
CHECK_RETVAL(arc_cache_invalidate(target));
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -205,6 +225,9 @@ static int arc_mem_read_block(struct target *target, target_addr_t addr,
|
|||
assert(!(addr & 3));
|
||||
assert(size == 4);
|
||||
|
||||
/* Flush cache before memory access */
|
||||
CHECK_RETVAL(arc_cache_flush(target));
|
||||
|
||||
CHECK_RETVAL(arc_jtag_read_memory(&arc->jtag_info, addr, count, buf,
|
||||
arc_mem_is_slow_memory(arc, addr, size, count)));
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user