cortex_a :apb mem read/write working with mmu_on
Conflicts: src/target/cortex_a.c
This commit is contained in:
Michel JAOUEN
Øyvind Harboe
parent
28ddd16ddc
commit
08303f10aa
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@ -320,6 +320,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
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/* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
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retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
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&dscr);
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if (retval != ERROR_OK)
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return retval;
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}
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@ -1449,6 +1450,94 @@ static int cortex_a8_deassert_reset(struct target *target)
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return ERROR_OK;
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}
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static int cortex_a8_write_apb_ab_memory(struct target *target,
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uint32_t address, uint32_t size,
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uint32_t count, const uint8_t *buffer)
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{
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int retval = ERROR_INVALID_ARGUMENTS;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm *armv4_5 = &armv7a->armv4_5_common;
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int nbytes = count * size;
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uint32_t data;
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struct reg *reg;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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reg = arm_reg_current(armv4_5, 0);
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reg->dirty = 1;
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reg = arm_reg_current(armv4_5, 1);
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reg->dirty = 1;
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retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
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if (retval != ERROR_OK)
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return retval;
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while (nbytes > 0) {
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data = *buffer++;
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retval = cortex_a8_dap_write_coreregister_u32(target, data, 1);
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if (retval != ERROR_OK)
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return retval;
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/* execute instruction STRB r1, [r0], 1 (0xe4c01001) */
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retval = cortex_a8_exec_opcode(target, ARMV4_5_STRB_IP(1, 0) , NULL);
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if (retval != ERROR_OK)
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return retval;
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--nbytes;
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}
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return retval;
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}
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static int cortex_a8_read_apb_ab_memory(struct target *target,
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uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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int retval = ERROR_INVALID_ARGUMENTS;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm *armv4_5 = &armv7a->armv4_5_common;
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/* read memory through APB-AP */
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int nbytes = count * size;
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uint32_t data;
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struct reg *reg;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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reg = arm_reg_current(armv4_5, 0);
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reg->dirty = 1;
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reg = arm_reg_current(armv4_5, 1);
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reg->dirty = 1;
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retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
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if (retval != ERROR_OK)
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return retval;
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while (nbytes > 0) {
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/* execute instruction LDRB r1, [r0], 1 (0xe4d01001) */
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retval = cortex_a8_exec_opcode(target, ARMV4_5_LDRB_IP(1, 0) , NULL);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_read_coreregister_u32(target, &data, 1);
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if (retval != ERROR_OK)
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return retval;
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*buffer++ = data;
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--nbytes;
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}
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return retval;
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}
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/*
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* Cortex-A8 Memory access
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*
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@ -1464,8 +1553,8 @@ static int cortex_a8_read_phys_memory(struct target *target,
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struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
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int retval = ERROR_INVALID_ARGUMENTS;
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uint8_t apsel = swjdp->apsel;
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LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", address, size, count);
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LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d",
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address, size, count);
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if (count && buffer) {
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@ -1474,115 +1563,75 @@ static int cortex_a8_read_phys_memory(struct target *target,
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/* read memory through AHB-AP */
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switch (size) {
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case 4:
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retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap,
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buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap,
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buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap,
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buffer, count, address);
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break;
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case 4:
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retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap,
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buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap,
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buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap,
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buffer, count, address);
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break;
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}
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} else {
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/* read memory through APB-AP */
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uint32_t saved_r0, saved_r1;
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int nbytes = count * size;
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uint32_t data;
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int enabled = 0;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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retval = cortex_a8_mmu(target, &enabled);
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if (retval != ERROR_OK)
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return retval;
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if (enabled)
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{
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LOG_WARNING("Reading physical memory through APB with MMU enabled is not yet implemented");
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LOG_WARNING("Reading physical memory through \
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APB with MMU enabled is not yet implemented");
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return ERROR_TARGET_FAILURE;
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}
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/* save registers r0 and r1, we are going to corrupt them */
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retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r0, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r1, 1);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
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if (retval != ERROR_OK)
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return retval;
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while (nbytes > 0) {
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/* execute instruction LDRB r1, [r0], 1 (0xe4d01001) */
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retval = cortex_a8_exec_opcode(target, ARMV4_5_LDRB_IP(1, 0) , NULL);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_read_coreregister_u32(target, &data, 1);
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if (retval != ERROR_OK)
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return retval;
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*buffer++ = data;
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--nbytes;
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}
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/* restore corrupted registers r0 and r1 */
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retval = cortex_a8_dap_write_coreregister_u32(target, saved_r0, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_write_coreregister_u32(target, saved_r1, 1);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer);
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}
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}
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return retval;
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}
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static int cortex_a8_read_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int enabled = 0;
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uint32_t virt, phys;
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int retval;
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int enabled = 0;
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uint32_t virt, phys;
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int retval;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
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uint8_t apsel = swjdp->apsel;
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/* cortex_a8 handles unaligned memory access */
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LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address,
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size, count);
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if (apsel == swjdp_memoryap) {
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retval = cortex_a8_mmu(target, &enabled);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count);
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retval = cortex_a8_mmu(target, &enabled);
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if (retval != ERROR_OK)
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return retval;
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if(enabled)
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{
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virt = address;
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retval = cortex_a8_virt2phys(target, virt, &phys);
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if (retval != ERROR_OK)
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return retval;
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if(enabled)
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{
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virt = address;
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retval = cortex_a8_virt2phys(target, virt, &phys);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", virt, phys);
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address = phys;
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}
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return cortex_a8_read_phys_memory(target, address, size, count, buffer);
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LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x",
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virt, phys);
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address = phys;
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}
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retval = cortex_a8_read_phys_memory(target, address, size, count, buffer);
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} else {
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retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer);
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}
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return retval;
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}
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static int cortex_a8_write_phys_memory(struct target *target,
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@ -1594,7 +1643,8 @@ static int cortex_a8_write_phys_memory(struct target *target,
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int retval = ERROR_INVALID_ARGUMENTS;
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uint8_t apsel = swjdp->apsel;
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LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, size, count);
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LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address,
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size, count);
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if (count && buffer) {
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@ -1620,69 +1670,19 @@ static int cortex_a8_write_phys_memory(struct target *target,
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} else {
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/* write memory through APB-AP */
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uint32_t saved_r0, saved_r1;
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int nbytes = count * size;
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uint32_t data;
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int enabled = 0;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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retval = cortex_a8_mmu(target, &enabled);
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if (retval != ERROR_OK)
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return retval;
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if (enabled)
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{
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LOG_WARNING("Writing physical memory through APB with MMU enabled is not yet implemented");
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LOG_WARNING("Writing physical memory through APB with MMU" \
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"enabled is not yet implemented");
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return ERROR_TARGET_FAILURE;
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}
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/* save registers r0 and r1, we are going to corrupt them */
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retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r0, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r1, 1);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
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if (retval != ERROR_OK)
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return retval;
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while (nbytes > 0) {
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data = *buffer++;
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retval = cortex_a8_dap_write_coreregister_u32(target, data, 1);
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if (retval != ERROR_OK)
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return retval;
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/* execute instruction STRB r1, [r0], 1 (0xe4c01001) */
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retval = cortex_a8_exec_opcode(target, ARMV4_5_STRB_IP(1, 0) , NULL);
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if (retval != ERROR_OK)
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return retval;
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--nbytes;
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}
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/* restore corrupted registers r0 and r1 */
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retval = cortex_a8_dap_write_coreregister_u32(target, saved_r0, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_write_coreregister_u32(target, saved_r1, 1);
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if (retval != ERROR_OK)
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return retval;
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/* we can return here without invalidating D/I-cache because */
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/* access through APB maintains cache coherency */
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return retval;
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return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer);
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}
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}
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@ -1750,27 +1750,39 @@ static int cortex_a8_write_phys_memory(struct target *target,
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static int cortex_a8_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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int enabled = 0;
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uint32_t virt, phys;
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int retval;
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int enabled = 0;
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uint32_t virt, phys;
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int retval;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
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uint8_t apsel = swjdp->apsel;
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/* cortex_a8 handles unaligned memory access */
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LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address,
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size, count);
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if (apsel == swjdp_memoryap) {
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LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
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retval = cortex_a8_mmu(target, &enabled);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
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retval = cortex_a8_mmu(target, &enabled);
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if (retval != ERROR_OK)
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return retval;
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if(enabled)
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{
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virt = address;
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retval = cortex_a8_virt2phys(target, virt, &phys);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys);
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address = phys;
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}
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if(enabled)
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{
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virt = address;
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retval = cortex_a8_virt2phys(target, virt, &phys);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys);
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address = phys;
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}
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return cortex_a8_write_phys_memory(target, address, size,
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count, buffer);
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retval = cortex_a8_write_phys_memory(target, address, size,
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count, buffer);
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}
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else {
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retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer);
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}
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return retval;
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}
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static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
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