target: "mcr" and "mrc" are ARM-specific
Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
209a0197f0
commit
177bbd8891
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@ -1219,6 +1219,13 @@ static int arm11_remove_watchpoint(struct target *target,
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return ERROR_FAIL;
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}
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static int arm11_mrc(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm, uint32_t *value);
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static int arm11_mcr(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2, uint32_t CRn,
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uint32_t CRm, uint32_t value);
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static int arm11_target_create(struct target *target, Jim_Interp *interp)
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{
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struct arm11_common *arm11;
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@ -1238,6 +1245,9 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
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armv4_5_init_arch_info(target, &arm11->arm);
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arm11->arm.mrc = arm11_mrc;
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arm11->arm.mcr = arm11_mcr;
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arm11->target = target;
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arm11->jtag_info.tap = target->tap;
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@ -1679,7 +1689,4 @@ struct target_type arm11_target = {
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.target_create = arm11_target_create,
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.init_target = arm11_init_target,
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.examine = arm11_examine,
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.mrc = arm11_mrc,
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.mcr = arm11_mcr,
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};
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@ -378,11 +378,24 @@ static int arm720t_init_target(struct command_context *cmd_ctx, struct target *t
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return arm7tdmi_init_target(cmd_ctx, target);
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}
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/* FIXME remove forward decls */
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static int arm720t_mrc(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value);
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static int arm720t_mcr(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value);
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static int arm720t_init_arch_info(struct target *target,
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struct arm720t_common *arm720t, struct jtag_tap *tap)
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{
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struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
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arm7_9->armv4_5_common.mrc = arm720t_mrc;
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arm7_9->armv4_5_common.mcr = arm720t_mcr;
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arm7tdmi_init_arch_info(target, arm7_9, tap);
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arm720t->common_magic = ARM720T_COMMON_MAGIC;
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@ -556,6 +569,4 @@ struct target_type arm720t_target =
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.target_create = arm720t_target_create,
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.init_target = arm720t_init_target,
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.examine = arm7_9_examine,
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.mrc = arm720t_mrc,
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.mcr = arm720t_mcr,
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};
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@ -624,10 +624,23 @@ int arm920t_soft_reset_halt(struct target *target)
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return ERROR_OK;
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}
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/* FIXME remove forward decls */
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static int arm920t_mrc(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value);
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static int arm920t_mcr(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value);
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int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
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{
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struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
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arm7_9->armv4_5_common.mrc = arm920t_mrc;
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arm7_9->armv4_5_common.mcr = arm920t_mcr;
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/* initialize arm7/arm9 specific info (including armv4_5) */
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arm9tdmi_init_arch_info(target, arm7_9, tap);
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@ -1452,6 +1465,4 @@ struct target_type arm920t_target =
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.target_create = arm920t_target_create,
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.init_target = arm9tdmi_init_target,
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.examine = arm7_9_examine,
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.mrc = arm920t_mrc,
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.mcr = arm920t_mcr,
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};
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@ -673,6 +673,9 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
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{
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struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
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arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
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arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
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/* initialize arm7/arm9 specific info (including armv4_5) */
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arm9tdmi_init_arch_info(target, arm7_9, tap);
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@ -822,6 +825,4 @@ struct target_type arm926ejs_target =
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.read_phys_memory = arm926ejs_read_phys_memory,
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.write_phys_memory = arm926ejs_write_phys_memory,
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.mrc = arm926ejs_mrc,
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.mcr = arm926ejs_mcr,
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};
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@ -790,6 +790,137 @@ usage:
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return retval;
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}
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static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
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{
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struct command_context *context;
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struct target *target;
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struct arm *arm;
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int retval;
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context = Jim_GetAssocData(interp, "context");
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if (context == NULL) {
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LOG_ERROR("%s: no command context", __func__);
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return JIM_ERR;
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}
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target = get_current_target(context);
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if (target == NULL) {
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LOG_ERROR("%s: no current target", __func__);
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return JIM_ERR;
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}
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if (!target_was_examined(target)) {
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LOG_ERROR("%s: not yet examined", target_name(target));
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return JIM_ERR;
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}
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arm = target_to_arm(target);
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if (!is_arm(arm)) {
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LOG_ERROR("%s: not an ARM", target_name(target));
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return JIM_ERR;
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}
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if ((argc < 6) || (argc > 7)) {
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/* FIXME use the command name to verify # params... */
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LOG_ERROR("%s: wrong number of arguments", __func__);
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return JIM_ERR;
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}
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int cpnum;
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uint32_t op1;
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uint32_t op2;
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uint32_t CRn;
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uint32_t CRm;
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uint32_t value;
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long l;
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/* NOTE: parameter sequence matches ARM instruction set usage:
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* MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
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* MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
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* The "rX" is necessarily omitted; it uses Tcl mechanisms.
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*/
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retval = Jim_GetLong(interp, argv[1], &l);
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if (retval != JIM_OK)
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return retval;
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if (l & ~0xf) {
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LOG_ERROR("%s: %s %d out of range", __func__,
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"coprocessor", (int) l);
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return JIM_ERR;
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}
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cpnum = l;
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retval = Jim_GetLong(interp, argv[2], &l);
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if (retval != JIM_OK)
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return retval;
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if (l & ~0x7) {
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LOG_ERROR("%s: %s %d out of range", __func__,
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"op1", (int) l);
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return JIM_ERR;
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}
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op1 = l;
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retval = Jim_GetLong(interp, argv[3], &l);
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if (retval != JIM_OK)
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return retval;
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if (l & ~0xf) {
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LOG_ERROR("%s: %s %d out of range", __func__,
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"CRn", (int) l);
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return JIM_ERR;
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}
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CRn = l;
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retval = Jim_GetLong(interp, argv[4], &l);
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if (retval != JIM_OK)
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return retval;
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if (l & ~0xf) {
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LOG_ERROR("%s: %s %d out of range", __func__,
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"CRm", (int) l);
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return JIM_ERR;
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}
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CRm = l;
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retval = Jim_GetLong(interp, argv[5], &l);
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if (retval != JIM_OK)
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return retval;
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if (l & ~0x7) {
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LOG_ERROR("%s: %s %d out of range", __func__,
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"op2", (int) l);
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return JIM_ERR;
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}
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op2 = l;
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value = 0;
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/* FIXME don't assume "mrc" vs "mcr" from the number of params;
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* that could easily be a typo! Check both...
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*
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* FIXME change the call syntax here ... simplest to just pass
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* the MRC() or MCR() instruction to be executed. That will also
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* let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
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* if that's ever needed.
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*/
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if (argc == 7) {
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retval = Jim_GetLong(interp, argv[6], &l);
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if (retval != JIM_OK) {
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return retval;
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}
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value = l;
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/* NOTE: parameters reordered! */
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// ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2)
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retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
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if (retval != ERROR_OK)
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return JIM_ERR;
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} else {
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/* NOTE: parameters reordered! */
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// ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2)
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retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
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if (retval != ERROR_OK)
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return JIM_ERR;
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Jim_SetResult(interp, Jim_NewIntObj(interp, value));
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}
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return JIM_OK;
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}
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static const struct command_registration arm_exec_command_handlers[] = {
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{
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.name = "reg",
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@ -811,6 +942,20 @@ static const struct command_registration arm_exec_command_handlers[] = {
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.usage = "<address> [<count> ['thumb']]",
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.help = "disassemble instructions ",
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},
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{
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.name = "mcr",
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.mode = COMMAND_EXEC,
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.jim_handler = &jim_mcrmrc,
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.help = "write coprocessor register",
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.usage = "cpnum op1 CRn op2 CRm value",
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},
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{
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.name = "mrc",
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.jim_handler = &jim_mcrmrc,
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.help = "read coprocessor register",
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.usage = "cpnum op1 CRn op2 CRm",
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},
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COMMAND_REGISTRATION_DONE
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};
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const struct command_registration arm_command_handlers[] = {
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@ -1252,6 +1397,24 @@ static int arm_full_context(struct target *target)
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return retval;
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}
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static int arm_default_mrc(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value)
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{
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LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
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return ERROR_FAIL;
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}
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static int arm_default_mcr(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value)
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{
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LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
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return ERROR_FAIL;
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}
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int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
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{
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target->arch_info = armv4_5;
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@ -1267,5 +1430,10 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
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if (!armv4_5->full_context && armv4_5->read_core_reg)
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armv4_5->full_context = arm_full_context;
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if (!armv4_5->mrc)
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armv4_5->mrc = arm_default_mrc;
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if (!armv4_5->mcr)
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armv4_5->mcr = arm_default_mcr;
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return ERROR_OK;
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}
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@ -112,11 +112,26 @@ struct arm
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/** Handle for the Embedded Trace Module, if one is present. */
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struct etm_context *etm;
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/* FIXME all these methods should take "struct arm *" not target */
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int (*full_context)(struct target *target);
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int (*read_core_reg)(struct target *target, struct reg *reg,
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int num, enum armv4_5_mode mode);
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int (*write_core_reg)(struct target *target, struct reg *reg,
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int num, enum armv4_5_mode mode, uint32_t value);
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/** Read coprocessor register. */
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int (*mrc)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value);
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/* Write coprocessor register. */
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int (*mcr)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value);
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void *arch_info;
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};
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@ -936,7 +936,7 @@ static void cortex_a8_post_debug_entry(struct target *target)
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int retval;
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/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
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retval = target->type->mrc(target, 15,
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retval = armv7a->armv4_5_common.mrc(target, 15,
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0, 0, /* op1, op2 */
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1, 0, /* CRn, CRm */
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&cortex_a8->cp15_control_reg);
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@ -947,7 +947,7 @@ static void cortex_a8_post_debug_entry(struct target *target)
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uint32_t cache_type_reg;
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/* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
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retval = target->type->mrc(target, 15,
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retval = armv7a->armv4_5_common.mrc(target, 15,
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0, 1, /* op1, op2 */
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0, 0, /* CRn, CRm */
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&cache_type_reg);
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@ -1535,6 +1535,7 @@ static int cortex_a8_examine_first(struct target *target)
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LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
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LOG_DEBUG("didr = 0x%08" PRIx32, didr);
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armv7a->armv4_5_common.core_type = ARM_MODE_MON;
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cortex_a8_dpm_setup(cortex_a8, didr);
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/* Setup Breakpoint Register Pairs */
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@ -1611,6 +1612,9 @@ static int cortex_a8_init_arch_info(struct target *target,
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cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
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armv4_5->arch_info = armv7a;
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armv4_5->mrc = cortex_a8_mrc,
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armv4_5->mcr = cortex_a8_mcr,
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/* prepare JTAG information for the new target */
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cortex_a8->jtag_info.tap = tap;
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cortex_a8->jtag_info.scann_size = 4;
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@ -1626,7 +1630,6 @@ static int cortex_a8_init_arch_info(struct target *target,
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cortex_a8->fast_reg_read = 0;
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/* register arch-specific functions */
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armv7a->examine_debug_reason = NULL;
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@ -1752,6 +1755,4 @@ struct target_type cortexa8_target = {
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.target_create = cortex_a8_target_create,
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.init_target = cortex_a8_init_target,
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.examine = cortex_a8_examine,
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.mrc = cortex_a8_mrc,
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.mcr = cortex_a8_mcr,
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};
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@ -44,8 +44,6 @@
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#include "jtag.h"
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static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv);
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static int target_array2mem(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv);
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static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv);
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@ -665,84 +663,6 @@ static void target_reset_examined(struct target *target)
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target->examined = false;
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}
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static int default_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
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{
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LOG_ERROR("Not implemented: %s", __func__);
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return ERROR_FAIL;
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}
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static int default_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
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{
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LOG_ERROR("Not implemented: %s", __func__);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
static int arm_cp_check(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
|
||||
{
|
||||
/* basic check */
|
||||
if (!target_was_examined(target))
|
||||
{
|
||||
LOG_ERROR("Target not examined yet");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if ((cpnum <0) || (cpnum > 15))
|
||||
{
|
||||
LOG_ERROR("Illegal co-processor %d", cpnum);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (op1 > 7)
|
||||
{
|
||||
LOG_ERROR("Illegal op1");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (op2 > 7)
|
||||
{
|
||||
LOG_ERROR("Illegal op2");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (CRn > 15)
|
||||
{
|
||||
LOG_ERROR("Illegal CRn");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (CRm > 15)
|
||||
{
|
||||
LOG_ERROR("Illegal CRm");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int target_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = arm_cp_check(target, cpnum, op1, op2, CRn, CRm);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return target->type->mrc(target, cpnum, op1, op2, CRn, CRm, value);
|
||||
}
|
||||
|
||||
int target_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = arm_cp_check(target, cpnum, op1, op2, CRn, CRm);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return target->type->mcr(target, cpnum, op1, op2, CRn, CRm, value);
|
||||
}
|
||||
|
||||
static int
|
||||
err_read_phys_memory(struct target *target, uint32_t address,
|
||||
uint32_t size, uint32_t count, uint8_t *buffer)
|
||||
|
|
@ -781,39 +701,6 @@ int target_init(struct command_context *cmd_ctx)
|
|||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @todo MCR/MRC are ARM-specific; don't require them in
|
||||
* all targets, or for ARMs without coprocessors.
|
||||
*/
|
||||
if (target->type->mcr == NULL)
|
||||
{
|
||||
target->type->mcr = default_mcr;
|
||||
} else
|
||||
{
|
||||
const struct command_registration mcr_cmd = {
|
||||
.name = "mcr",
|
||||
.mode = COMMAND_EXEC,
|
||||
.jim_handler = &jim_mcrmrc,
|
||||
.help = "write coprocessor",
|
||||
.usage = "<cpnum> <op1> <op2> <CRn> <CRm> <value>",
|
||||
};
|
||||
register_command(cmd_ctx, NULL, &mcr_cmd);
|
||||
}
|
||||
|
||||
if (target->type->mrc == NULL)
|
||||
{
|
||||
target->type->mrc = default_mrc;
|
||||
} else
|
||||
{
|
||||
const struct command_registration mrc_cmd = {
|
||||
.name = "mrc",
|
||||
.jim_handler = &jim_mcrmrc,
|
||||
.help = "read coprocessor",
|
||||
.usage = "<cpnum> <op1> <op2> <CRn> <CRm>",
|
||||
};
|
||||
register_command(cmd_ctx, NULL, &mrc_cmd);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @todo get rid of those *memory_imp() methods, now that all
|
||||
|
|
@ -4883,92 +4770,6 @@ COMMAND_HANDLER(handle_fast_load_command)
|
|||
return retval;
|
||||
}
|
||||
|
||||
static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
|
||||
{
|
||||
struct command_context *context;
|
||||
struct target *target;
|
||||
int retval;
|
||||
|
||||
context = Jim_GetAssocData(interp, "context");
|
||||
if (context == NULL) {
|
||||
LOG_ERROR("array2mem: no command context");
|
||||
return JIM_ERR;
|
||||
}
|
||||
target = get_current_target(context);
|
||||
if (target == NULL) {
|
||||
LOG_ERROR("array2mem: no current target");
|
||||
return JIM_ERR;
|
||||
}
|
||||
|
||||
if ((argc < 6) || (argc > 7))
|
||||
{
|
||||
return JIM_ERR;
|
||||
}
|
||||
|
||||
int cpnum;
|
||||
uint32_t op1;
|
||||
uint32_t op2;
|
||||
uint32_t CRn;
|
||||
uint32_t CRm;
|
||||
uint32_t value;
|
||||
|
||||
int e;
|
||||
long l;
|
||||
e = Jim_GetLong(interp, argv[1], &l);
|
||||
if (e != JIM_OK) {
|
||||
return e;
|
||||
}
|
||||
cpnum = l;
|
||||
|
||||
e = Jim_GetLong(interp, argv[2], &l);
|
||||
if (e != JIM_OK) {
|
||||
return e;
|
||||
}
|
||||
op1 = l;
|
||||
|
||||
e = Jim_GetLong(interp, argv[3], &l);
|
||||
if (e != JIM_OK) {
|
||||
return e;
|
||||
}
|
||||
CRn = l;
|
||||
|
||||
e = Jim_GetLong(interp, argv[4], &l);
|
||||
if (e != JIM_OK) {
|
||||
return e;
|
||||
}
|
||||
CRm = l;
|
||||
|
||||
e = Jim_GetLong(interp, argv[5], &l);
|
||||
if (e != JIM_OK) {
|
||||
return e;
|
||||
}
|
||||
op2 = l;
|
||||
|
||||
value = 0;
|
||||
|
||||
if (argc == 7)
|
||||
{
|
||||
e = Jim_GetLong(interp, argv[6], &l);
|
||||
if (e != JIM_OK) {
|
||||
return e;
|
||||
}
|
||||
value = l;
|
||||
|
||||
retval = target_mcr(target, cpnum, op1, op2, CRn, CRm, value);
|
||||
if (retval != ERROR_OK)
|
||||
return JIM_ERR;
|
||||
} else
|
||||
{
|
||||
retval = target_mrc(target, cpnum, op1, op2, CRn, CRm, &value);
|
||||
if (retval != ERROR_OK)
|
||||
return JIM_ERR;
|
||||
|
||||
Jim_SetResult(interp, Jim_NewIntObj(interp, value));
|
||||
}
|
||||
|
||||
return JIM_OK;
|
||||
}
|
||||
|
||||
static const struct command_registration target_command_handlers[] = {
|
||||
{
|
||||
.name = "targets",
|
||||
|
|
|
|||
|
|
@ -213,11 +213,6 @@ struct target_type
|
|||
|
||||
int (*mmu)(struct target *target, int *enabled);
|
||||
|
||||
/* Read coprocessor - arm specific. Default implementation returns error. */
|
||||
int (*mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
|
||||
|
||||
/* Write coprocessor. Default implementation returns error. */
|
||||
int (*mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
|
||||
};
|
||||
|
||||
#endif // TARGET_TYPE_H
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user