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pic32mx: 0 wait state option 

By default pic32mx starts after any reset with 1 wait state for RAM access/exec.
It can be changed to 0 wait states by clearing the BMXWSDRM bit (bit 6) in BMXCON register.
With 0 wait states near doubles the execution speed. CRC check sum can be done much faster
increasing verify_image speed. Fast data transfer also works with a bit higher scan rate, up to 1500 Khz.
This option can be set at any time with
mww 0xbf882004 0x40
or cleared with
mww 0xbf882008 0x40.
Some numbers for FTDI/HS with current devel code and a elf file:

Core clock / wait states	             verify_image speed
------------------------------------|------------------------------

        4 Mhz    /    1                            21 KiB/s
        4 Mhz    /    0                            36 KiB/s
        8 Mhz    /    1                            37 KiB/s
        8 Mhz    /    0                            57 KiB/s

Change-Id: I4092ad0f3753f72f77108718d0ed3a3ab84e3b23
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1141
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
This commit is contained in:
Salvador Arroyo 2013-02-23 20:00:21 +01:00 committed by Spencer Oliver
parent c185a5b724
commit 1d040adb0d
1 changed files with 2 additions and 3 deletions
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5
tcl/target/pic32mx.cfg
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@ -50,12 +50,11 @@ $_TARGETNAME configure -event reset-init {
# from reset the pic32 cannot execute code in ram - enable ram execution
# minimum offset from start of ram is 2k
#
global _PIC32MX_DATASIZE
global _WORKAREASIZE
# BMXCON
mww 0xbf882000 0x001f0040
# BMXCON set 0 wait state option by clearing BMXWSDRM bit, bit 6
mww 0xbf882000 0x001f0000
# BMXDKPBA: 2k kernel data @ 0xa0000000
mww 0xbf882010 $_PIC32MX_DATASIZE
# BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)