ADIv5: use new dap_run() operation
Make ADIv5 use one of the new transport-neutral interfaces: call dap_run(), not jtagdp_transaction_endcheck(). Also, make that old interface private; and bugfix some of its call sites to handle the fault returns, instead of ignoring them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
db6c994642
commit
24b1426a72
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@ -213,7 +213,7 @@ static int adi_jtag_scan_inout_check_u32(struct swjdp_common *swjdp,
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return retval;
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}
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int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
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static int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
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{
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int retval;
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uint32_t ctrlstat;
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@ -277,7 +277,7 @@ int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
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adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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if ((retval = dap_run(swjdp)) != ERROR_OK)
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return retval;
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swjdp->ack = swjdp->ack & 0x7;
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}
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@ -323,20 +323,20 @@ int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
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| SSTICKYERR, NULL);
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adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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if ((retval = dap_run(swjdp)) != ERROR_OK)
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return retval;
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LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
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dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
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dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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if ((retval = dap_run(swjdp)) != ERROR_OK)
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return retval;
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LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
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PRIx32, mem_ap_csw, mem_ap_tar);
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}
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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if ((retval = dap_run(swjdp)) != ERROR_OK)
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return retval;
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return ERROR_JTAG_DEVICE_ERROR;
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}
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@ -561,7 +561,7 @@ int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
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if (retval != ERROR_OK)
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return retval;
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return jtagdp_transaction_endcheck(swjdp);
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return dap_run(swjdp);
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}
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/**
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@ -611,7 +611,7 @@ int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
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if (retval != ERROR_OK)
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return retval;
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return jtagdp_transaction_endcheck(swjdp);
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return dap_run(swjdp);
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}
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/*****************************************************************************
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@ -667,7 +667,7 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
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}
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if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
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if (dap_run(swjdp) == ERROR_OK)
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{
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wcount = wcount - blocksize;
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address = address + 4 * blocksize;
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@ -681,6 +681,7 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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if (errorcount > 1)
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{
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LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
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/* REVISIT return the *actual* fault code */
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return ERROR_JTAG_DEVICE_ERROR;
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}
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}
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@ -744,11 +745,12 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
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memcpy(&outvalue, buffer, sizeof(uint32_t));
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dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
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if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
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if (dap_run(swjdp) != ERROR_OK)
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{
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LOG_WARNING("Block write error address "
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"0x%" PRIx32 ", count 0x%x",
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address, count);
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/* REVISIT return *actual* fault code */
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return ERROR_JTAG_DEVICE_ERROR;
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}
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}
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@ -777,7 +779,10 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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memcpy(&svalue, buffer, sizeof(uint16_t));
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uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
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dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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break;
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count -= 2;
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address += 2;
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buffer += 2;
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@ -837,11 +842,12 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
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memcpy(&outvalue, buffer, sizeof(uint32_t));
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dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
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if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
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if (dap_run(swjdp) != ERROR_OK)
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{
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LOG_WARNING("Block write error address "
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"0x%" PRIx32 ", count 0x%x",
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address, count);
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/* REVISIT return *actual* fault code */
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return ERROR_JTAG_DEVICE_ERROR;
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}
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}
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@ -868,7 +874,10 @@ int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
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uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
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dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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break;
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count--;
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address++;
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buffer++;
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@ -933,7 +942,7 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
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adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
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DPAP_READ, 0, buffer + 4 * readcount,
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&swjdp->ack);
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if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
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if (dap_run(swjdp) == ERROR_OK)
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{
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wcount = wcount - blocksize;
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address += 4 * blocksize;
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@ -948,6 +957,7 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
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{
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LOG_WARNING("Block read error address 0x%" PRIx32
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", count 0x%x", address, count);
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/* REVISIT return the *actual* fault code */
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return ERROR_JTAG_DEVICE_ERROR;
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}
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}
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@ -1002,9 +1012,10 @@ static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
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do
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{
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dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
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if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
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if (dap_run(swjdp) != ERROR_OK)
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{
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LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
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/* REVISIT return the *actual* fault code */
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return ERROR_JTAG_DEVICE_ERROR;
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}
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@ -1046,7 +1057,10 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer,
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{
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dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
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dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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break;
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if (address & 0x1)
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{
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for (i = 0; i < 2; i++)
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@ -1100,9 +1114,10 @@ static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
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do
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{
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dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
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if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
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if (dap_run(swjdp) != ERROR_OK)
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{
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LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
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/* REVISIT return the *actual* fault code */
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return ERROR_JTAG_DEVICE_ERROR;
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}
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@ -1144,7 +1159,10 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer,
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{
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dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
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dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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break;
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*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
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count--;
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address++;
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@ -1297,7 +1315,7 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
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dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
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dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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if ((retval = dap_run(swjdp)) != ERROR_OK)
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return retval;
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/* Check that we have debug power domains activated */
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@ -1305,7 +1323,7 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
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{
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LOG_DEBUG("DAP: wait CDBGPWRUPACK");
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dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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if ((retval = dap_run(swjdp)) != ERROR_OK)
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return retval;
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alive_sleep(10);
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}
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@ -1314,7 +1332,7 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
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{
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LOG_DEBUG("DAP: wait CSYSPWRUPACK");
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dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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if ((retval = dap_run(swjdp)) != ERROR_OK)
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return retval;
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alive_sleep(10);
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}
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@ -1362,7 +1380,7 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
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int dap_info_command(struct command_context *cmd_ctx,
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struct swjdp_common *swjdp, int apsel)
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{
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int retval;
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uint32_t dbgbase, apid;
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int romtable_present = 0;
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uint8_t mem_ap;
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@ -1376,7 +1394,10 @@ int dap_info_command(struct command_context *cmd_ctx,
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
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dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
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jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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return retval;
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/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
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mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
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command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
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@ -1428,7 +1449,10 @@ int dap_info_command(struct command_context *cmd_ctx,
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mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
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mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
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mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
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jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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return retval;
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if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
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command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
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", CID2 0x%2.2" PRIx32
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@ -1741,7 +1765,10 @@ DAP_COMMAND_HANDLER(dap_baseaddr_command)
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* use the ID register to verify it's a MEM-AP.
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*/
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dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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return retval;
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command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
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if (apselsave != apsel)
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@ -1793,7 +1820,10 @@ DAP_COMMAND_HANDLER(dap_apsel_command)
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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return retval;
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command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
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apsel, apid);
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@ -1824,7 +1854,10 @@ DAP_COMMAND_HANDLER(dap_apid_command)
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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return retval;
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command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
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if (apselsave != apsel)
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dap_ap_select(swjdp, apselsave);
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@ -355,9 +355,6 @@ int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
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int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
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uint32_t addr, uint32_t *value);
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/* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */
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int jtagdp_transaction_endcheck(struct swjdp_common *swjdp);
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/* Queued MEM-AP memory mapped single word transfers */
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int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
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int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
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@ -78,7 +78,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
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dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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/* restore DCB_DCRDR - this needs to be in a seperate
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* transaction otherwise the emulated DCC channel breaks */
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@ -107,7 +107,7 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
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dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
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retval = jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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/* restore DCB_DCRDR - this needs to be in a seperate
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* transaction otherwise the emulated DCC channel breaks */
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@ -179,6 +179,7 @@ static int cortex_m3_single_step_core(struct target *target)
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static int cortex_m3_endreset_event(struct target *target)
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{
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int i;
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int retval;
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uint32_t dcb_demcr;
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struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
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struct armv7m_common *armv7m = &cortex_m3->armv7m;
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@ -234,14 +235,16 @@ static int cortex_m3_endreset_event(struct target *target)
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target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
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dwt_list[i].function);
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}
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jtagdp_transaction_endcheck(swjdp);
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retval = dap_run(swjdp);
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if (retval != ERROR_OK)
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return retval;
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register_cache_invalidate(cortex_m3->armv7m.core_cache);
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/* make sure we have latest dhcsr flags */
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mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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return ERROR_OK;
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return retval;
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}
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static int cortex_m3_examine_debug_reason(struct target *target)
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@ -276,6 +279,7 @@ static int cortex_m3_examine_exception_reason(struct target *target)
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uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct swjdp_common *swjdp = &armv7m->swjdp_info;
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int retval;
|
||||
|
||||
mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
|
||||
switch (armv7m->exception_number)
|
||||
|
|
@ -313,10 +317,13 @@ static int cortex_m3_examine_exception_reason(struct target *target)
|
|||
except_sr = 0;
|
||||
break;
|
||||
}
|
||||
jtagdp_transaction_endcheck(swjdp);
|
||||
LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
|
||||
shcsr, except_sr, cfsr, except_ar);
|
||||
return ERROR_OK;
|
||||
retval = dap_run(swjdp);
|
||||
if (retval == ERROR_OK)
|
||||
LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
|
||||
", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
|
||||
armv7m_exception_string(armv7m->exception_number),
|
||||
shcsr, except_sr, cfsr, except_ar);
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* PSP is used in some thread modes */
|
||||
|
|
|
|||
Loading…
Reference in New Issue