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target/nds32_disassembler: fix format specifiers warnings 

According to the standard every operation returns at least an integer,
so PRIu8 format specifier is not suitable for these values as is.

This breaks build on OS X (x86_64-apple-darwin13.0.0) with "Apple LLVM
version 5.0 (clang-500.2.79) (based on LLVM 3.3svn)".

Fix by adding appropriate casts. In fact there's plenty of room (and
I'd say necessity) for factoring out common code in there, but it's
too invasive for a non-maintainer.

Change-Id: I7d2182eb1d2f86fa22c882fbbaa6cfadf1c3e8fc
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1878
Tested-by: jenkins
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Paul Fertser 2014-01-17 14:11:55 +04:00 committed by Spencer Oliver
parent 3e0f34b198
commit 279878ccd7
1 changed files with 13 additions and 13 deletions
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26
src/target/nds32_disassembler.c
View File

@ -2124,7 +2124,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMULTS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2139,7 +2139,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMULT64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2153,7 +2153,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMADDS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2167,7 +2167,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMADD64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2181,7 +2181,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMSUBS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2195,7 +2195,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMSUB64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2209,7 +2209,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tDIVS\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2223,7 +2223,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tDIV\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2237,7 +2237,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMULT32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2251,7 +2251,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMADD32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -2265,7 +2265,7 @@ static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32
"\tMSUB32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
address,
opcode, (dt_val >> 1) & 0x1, instruction->info.ra,
opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
instruction->info.rb);
}
break;
@ -3546,7 +3546,7 @@ static int nds32_parse_group_3_insn_16(struct nds32 *nds32, uint16_t opcode,
"0x%8.8" PRIx32 "\t0x%4.4" PRIx16
"\t\tBREAK16\t#%" PRId16,
address,
opcode, opcode & 0x1F);
opcode, (int16_t)(opcode & 0x1F));
} else { /* EX9.IT */
instruction->type = NDS32_INSN_MISC;
/* TODO: implement real instruction semantics */
@ -3555,7 +3555,7 @@ static int nds32_parse_group_3_insn_16(struct nds32 *nds32, uint16_t opcode,
"0x%8.8" PRIx32 "\t0x%4.4" PRIx16
"\t\tEX9.IT\t#%" PRId16,
address,
opcode, opcode & 0x1FF);
opcode, (int16_t)(opcode & 0x1FF));
}
break;
case 2: /* ADDI10S */