at91sam3s* support
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Olaf Lüke
Øyvind Harboe
parent
fb96b8607a
commit
2986320cde
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@ -2,6 +2,10 @@
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* Copyright (C) 2009 by Duane Ellis *
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* openocd@duaneellis.com *
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* *
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* Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
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* olaf@uni-paderborn.de *
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* *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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@ -63,9 +67,12 @@
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#define REG_NAME_WIDTH (12)
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// at91sam3u series (has one or two flash banks)
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#define FLASH_BANK0_BASE_U 0x00080000
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#define FLASH_BANK1_BASE_U 0x00100000
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#define FLASH_BANK0_BASE 0x00080000
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#define FLASH_BANK1_BASE 0x00100000
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// at91sam3s series (has always one flash bank)
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#define FLASH_BANK_BASE_S 0x00400000
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#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
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#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
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@ -254,6 +261,7 @@ get_current_sam3(struct command_context *cmd_ctx)
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// these are used to *initialize* the "pChip->details" structure.
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static const struct sam3_chip_details all_sam3_details[] = {
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// Start at91sam3u* series
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{
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.chipid_cidr = 0x28100960,
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.name = "at91sam3u4e",
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@ -284,7 +292,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE,
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.base_address = FLASH_BANK0_BASE_U,
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.controller_address = 0x400e0800,
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.present = 1,
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.size_bytes = 128 * 1024,
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@ -299,7 +307,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 1,
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.base_address = FLASH_BANK1_BASE,
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.base_address = FLASH_BANK1_BASE_U,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 128 * 1024,
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@ -333,7 +341,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE,
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.base_address = FLASH_BANK0_BASE_U,
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.controller_address = 0x400e0800,
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.present = 1,
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.size_bytes = 128 * 1024,
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@ -374,7 +382,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE,
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.base_address = FLASH_BANK0_BASE_U,
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.controller_address = 0x400e0800,
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.present = 1,
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.size_bytes = 64 * 1024,
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@ -422,7 +430,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE,
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.base_address = FLASH_BANK0_BASE_U,
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.controller_address = 0x400e0800,
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.present = 1,
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.size_bytes = 128 * 1024,
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@ -436,7 +444,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 1,
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.base_address = FLASH_BANK1_BASE,
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.base_address = FLASH_BANK1_BASE_U,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 128 * 1024,
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@ -470,7 +478,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE,
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.base_address = FLASH_BANK0_BASE_U,
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.controller_address = 0x400e0800,
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.present = 1,
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.size_bytes = 128 * 1024,
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@ -511,7 +519,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE,
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.base_address = FLASH_BANK0_BASE_U,
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.controller_address = 0x400e0800,
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.present = 1,
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.size_bytes = 64 * 1024,
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@ -529,6 +537,300 @@ static const struct sam3_chip_details all_sam3_details[] = {
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},
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},
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// Start at91sam3s* series
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// Note: The preliminary at91sam3s datasheet says on page 302
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// that the flash controller is at address 0x400E0800.
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// This is _not_ the case, the controller resides at address 0x400e0a0.
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{
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.chipid_cidr = 0x28A00960,
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.name = "at91sam3s4c",
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.total_flash_size = 256 * 1024,
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.total_sram_size = 48 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 256 * 1024,
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.nsectors = 32,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x28900960,
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.name = "at91sam3s4b",
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.total_flash_size = 256 * 1024,
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.total_sram_size = 48 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 256 * 1024,
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.nsectors = 32,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x28800960,
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.name = "at91sam3s4a",
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.total_flash_size = 256 * 1024,
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.total_sram_size = 48 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 256 * 1024,
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.nsectors = 32,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x28AA0760,
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.name = "at91sam3s2c",
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.total_flash_size = 128 * 1024,
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.total_sram_size = 32 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 128 * 1024,
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.nsectors = 16,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x289A0760,
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.name = "at91sam3s2b",
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.total_flash_size = 128 * 1024,
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.total_sram_size = 32 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 128 * 1024,
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.nsectors = 16,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x288A0760,
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.name = "at91sam3s2a",
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.total_flash_size = 128 * 1024,
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.total_sram_size = 32 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 128 * 1024,
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.nsectors = 16,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x28A90560,
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.name = "at91sam3s1c",
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.total_flash_size = 64 * 1024,
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.total_sram_size = 16 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 64 * 1024,
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.nsectors = 8,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x28990560,
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.name = "at91sam3s1b",
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.total_flash_size = 64 * 1024,
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.total_sram_size = 16 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 64 * 1024,
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.nsectors = 8,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x28890560,
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.name = "at91sam3s1a",
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.total_flash_size = 64 * 1024,
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.total_sram_size = 16 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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// .bank[0] = {
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.present = 1,
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.size_bytes = 64 * 1024,
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.nsectors = 8,
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.sector_size = 8192,
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.page_size = 256,
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},
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// .bank[1] = {
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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// terminate
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{
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.chipid_cidr = 0,
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@ -1648,23 +1950,34 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
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switch (bank->base) {
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default:
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LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
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LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
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[at91sam3u series] or 0x%08x [at91sam3s series])",
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((unsigned int)(bank->base)),
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((unsigned int)(FLASH_BANK0_BASE)),
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((unsigned int)(FLASH_BANK1_BASE)));
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((unsigned int)(FLASH_BANK0_BASE_U)),
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((unsigned int)(FLASH_BANK1_BASE_U)),
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((unsigned int)(FLASH_BANK_BASE_S)));
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return ERROR_FAIL;
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break;
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case FLASH_BANK0_BASE:
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// at91sam3u series
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case FLASH_BANK0_BASE_U:
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bank->driver_priv = &(pChip->details.bank[0]);
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bank->bank_number = 0;
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pChip->details.bank[0].pChip = pChip;
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pChip->details.bank[0].pBank = bank;
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break;
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case FLASH_BANK1_BASE:
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case FLASH_BANK1_BASE_U:
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bank->driver_priv = &(pChip->details.bank[1]);
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bank->bank_number = 1;
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pChip->details.bank[1].pChip = pChip;
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pChip->details.bank[1].pBank = bank;
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// at91sam3s series
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case FLASH_BANK_BASE_S:
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bank->driver_priv = &(pChip->details.bank[0]);
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bank->bank_number = 0;
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pChip->details.bank[0].pChip = pChip;
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pChip->details.bank[0].pBank = bank;
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break;
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}
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@ -0,0 +1,3 @@
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source [find target/at91sam3sXX.cfg]
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$_TARGETNAME configure -event gdb-attach { reset init }
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@ -0,0 +1,50 @@
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# script for ATMEL sam3, a CORTEX-M3 chip
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#
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# at91sam3u4e
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# at91sam3u2e
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# at91sam3u1e
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# at91sam3u4c
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# at91sam3u2c
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# at91sam3u1c
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#
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# at91sam3s4c
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# at91sam3s4b
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# at91sam3s4a
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# at91sam3s2c
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# at91sam3s2b
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# at91sam3s2a
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# at91sam3s1c
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# at91sam3s1b
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# at91sam3s1a
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME sam3
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}
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||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID ] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# 16K is plenty, the smallest chip has this much
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
|
||||
|
||||
$_TARGETNAME configure -event gdb-flash-erase-start {
|
||||
halt
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
# script for ATMEL sam3, a CORTEX-M3 chip
|
||||
#
|
||||
# at91sam3s4c
|
||||
# at91sam3s4b
|
||||
# at91sam3s4a
|
||||
# at91sam3s2c
|
||||
# at91sam3s2b
|
||||
# at91sam3s2a
|
||||
# at91sam3s1c
|
||||
# at91sam3s1b
|
||||
# at91sam3s1a
|
||||
|
||||
source [find target/at91sam3XXX.cfg]
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME
|
||||
|
|
@ -1,40 +1,11 @@
|
|||
# script for ATMEL sam3, a CORTEX-M3 chip
|
||||
#
|
||||
# at91sam3u4e
|
||||
# at91sam3u2e
|
||||
# at91sam3u1e
|
||||
# at91sam3u4c
|
||||
# at91sam3u2c
|
||||
# at91sam3u1c
|
||||
# at91sam3u4e
|
||||
# at91sam3u2e
|
||||
# at91sam3u1e
|
||||
# at91sam3u4c
|
||||
# at91sam3u2c
|
||||
# at91sam3u1c
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME sam3
|
||||
}
|
||||
source [find target/at91sam3XXX.cfg]
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID ] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# 16K is plenty, the smallest chip has this much
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
|
||||
|
||||
$_TARGETNAME configure -event gdb-flash-erase-start {
|
||||
halt
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue