Added timeout(instead of infinite loop) to soft_reset_halt

git-svn-id: svn://svn.berlios.de/openocd/trunk@533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2008-04-02 06:37:08 +00:00
parent b174a5b6a3
commit 2a2935573e
3 changed files with 51 additions and 9 deletions

View File

@ -365,14 +365,28 @@ int arm720t_soft_reset_halt(struct target_s *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
int i;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
target->type->halt(target);
while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
for (i=0; i<10; i++)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
} else
{
break;
}
/* do not eat all CPU, time out after 1 se*/
usleep(100*1000);
}
if (i==10)
{
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;

View File

@ -622,13 +622,27 @@ int arm920t_soft_reset_halt(struct target_s *target)
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int i;
target->type->halt(target);
while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
for (i=0; i<10; i++)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
} else
{
break;
}
/* do not eat all CPU, time out after 1 se*/
usleep(100*1000);
}
if (i==10)
{
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;

View File

@ -578,13 +578,27 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int i;
target->type->halt(target);
while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
for (i=0; i<10; i++)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
} else
{
break;
}
/* do not eat all CPU, time out after 1 se*/
usleep(100*1000);
}
if (i==10)
{
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;