tcl/target|board: add configs for Alphascale asm9260t

This adds configs for Alphascale asm9260t ARM based SoC and
Evaluation Kit based on this chip.

Change-Id: Id8d3a1ef204e3ae84540c2693e3d62650ba82f73
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2515
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Oleksij Rempel 2015-01-19 16:43:14 +01:00 committed by Paul Fertser
parent 41124ea992
commit 2b0beed4b1
2 changed files with 94 additions and 0 deletions

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source [find target/alphascale_asm9260t.cfg]
reset_config trst_and_srst
$_TARGETNAME configure -event reset-init {
echo "Configure clock"
# Enable SRAM clk
mww 0x80040024 0x4
# Enable IRQ clk
mww 0x80040034 0x100
# Enable DMA0,1 clk
mww 0x80040024 0x600
# Make sysre syspll is enabled
mww 0x80040238 0x750
#CPU = PLLCLK/2
mww 0x8004017C 0x2
#SYSAHBCLK = CPUCLK/2
mww 0x80040180 0x2
# Set PLL freq to 480MHz
mww 0x80040100 480
# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
sleep 100
# select PLL as main source
mww 0x80040120 0x1
# disable and enble main clk to update changes?
mww 0x80040124 0x0
mww 0x80040124 0x1
echo "Configure memory"
#enable EMI CLK
mww 0x80040024 0x40
# configure memory controller for internal SRAM
mww 0x80700000 0x1188
# change default emi clk delay
mww 0x8004034C 0xA0503
# make sure chip_select_register2_low has correct value (why?)
mww 0x8070001c 0x20000000
# set type to sdram and size to 32MB
mww 0x8070005c 0xa
# configure internal SDRAM timing
mww 0x80700004 0x024996d9
# configure Static Memory timing
mww 0x80700094 0x00542b4f
echo "Configure uart4"
# enable pinctrl clk
mww 0x80040024 0x2000000
# mux GPIO3_0 and GPIO3_1 to UART4
mww 0x80044060 0x2
mww 0x80044064 0x2
# configure UART4CLKDIV
mww 0x800401a8 0x1
# enable uart4 clk
mww 0x80040024 0x8000
# clear softrst and clkgate on uart4
mww 0x80010008 0xC0000000
# set bandrate 115200 12M
mww 0x80010030 0x00062070
# enable Rx&Tx
mww 0x80010024 0x301
# clear hw control
mww 0x80010028 0xc000
}
$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
$_TARGETNAME arm7_9 fast_memory_access enable
$_TARGETNAME arm7_9 dcc_downloads enable

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if { [info exists CHIPNAME] } {
set _CHIPNAME $_CHIPNAME
} else {
set _CHIPNAME asm9260t
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x079264F3
}
# And srst_pulls_trst by chip design.
reset_config srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME