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tcl/target/ls1088: Break out common configuration 

Several Layerscape processors (LS1088A, LS2088A, LS2160A, and LS1028A)
share a common architecture. Break out the common setup from the LS1088
config in preparation for adding the LS1028A. There's no official name
for this series of processors, but NXP refers to them as "chassis
generation 3" in U-Boot, so we'll go with that too.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ic6f89f95c678101f54579bcaa5d79c5b67ddf50a
Reviewed-on: https://review.openocd.org/c/openocd/+/6975
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Sean Anderson 2022-05-13 11:03:41 -04:00 committed by Antonio Borneo
parent 0a36acbf6a
commit 32b3859258
2 changed files with 65 additions and 55 deletions
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57
tcl/target/ls1088a.cfg
View File

@ -13,62 +13,9 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x5ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
set _CPUS 8
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
set _CPU_BASE 0x81000000
set _CPU_STRIDE 0x100000
set _CPU_DBGOFF 0x10000
set _CPU_CTIOFF 0x20000
set _TARGETS {}
for {set i 0} {$i < 8} {incr i} {
set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
{*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
lappend _TARGETS $_CHIPNAME.cpu$i
}
target smp {*}$_TARGETS
# Service processor
target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
# Normally you will not need to call this, but if you are using the hard-coded
# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
# instructions. This will cause the CPU to almost immediately execute an
# illegal instruction.
#
# This code is idempotent; releasing a released CPU has no effect, although it
# will halt/resume the service processor.
add_help_text release_cpu "Release a cpu which is held off"
proc release_cpu {cpu} {
set RST_BRRL 0x1e60060
set old [target current]
targets $::_CHIPNAME.sp
set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
if {$not_halted} {
halt
}
# Release the cpu; it will start executing something bogus
mem2array regs 32 $RST_BRRL 1
mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
if {$not_halted} {
resume
}
targets $old
}
targets $_CHIPNAME.cpu0
source [find target/lsch3_common.cfg]
# Seems to work OK in testing
adapter speed 10000

63
tcl/target/lsch3_common.cfg Normal file
View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This contains common configuration for NXP Layerscape chassis generation 3
if { ![info exists _CPUS] } {
error "_CPUS must be set to the number of cores"
}
jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
set _CPU_BASE 0x81000000
set _CPU_STRIDE 0x100000
set _CPU_DBGOFF 0x10000
set _CPU_CTIOFF 0x20000
set _TARGETS {}
for {set i 0} {$i < $_CPUS} {incr i} {
set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
{*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
lappend _TARGETS $_CHIPNAME.cpu$i
}
target smp {*}$_TARGETS
# Service processor
target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
# Normally you will not need to call this, but if you are using the hard-coded
# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
# instructions. This will cause the CPU to almost immediately execute an
# illegal instruction.
#
# This code is idempotent; releasing a released CPU has no effect, although it
# will halt/resume the service processor.
add_help_text release_cpu "Release a cpu which is held off"
proc release_cpu {cpu} {
set RST_BRRL 0x1e60060
set old [target current]
targets $::_CHIPNAME.sp
set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
if {$not_halted} {
halt
}
# Release the cpu; it will start executing something bogus
mem2array regs 32 $RST_BRRL 1
mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
if {$not_halted} {
resume
}
targets $old
}
targets $_CHIPNAME.cpu0