diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index befd28863..35d8275b5 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -100,18 +100,21 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
 	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
 		switch [$_chipname.tpiu cget -port-width] {
 			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
 				mmw 0xE0042004 0x00000060 0x000000c0
 				mmw 0x40021020 0x00000000 0x0000ff00
 				mmw 0x40021000 0x000000a0 0x000000f0
 				mmw 0x40021008 0x000000f0 0x00000000
 			  }
 			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
 				mmw 0xE0042004 0x000000a0 0x000000c0
 				mmw 0x40021020 0x00000000 0x000fff00
 				mmw 0x40021000 0x000002a0 0x000003f0
 				mmw 0x40021008 0x000003f0 0x00000000
 			  }
 			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
 				mmw 0xE0042004 0x000000e0 0x000000c0
 				mmw 0x40021020 0x00000000 0x0fffff00
 				mmw 0x40021000 0x00002aa0 0x00003ff0
@@ -119,6 +122,7 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
 			  }
 		}
 	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
 		mmw 0xE0042004 0x00000020 0x000000c0
 	}
 }
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 61d25b7c3..9a696736c 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -110,18 +110,21 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
 	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
 		switch [$_chipname.tpiu cget -port-width] {
 			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
 				mmw 0xE0042004 0x00000060 0x000000c0
 				mmw 0x48001020 0x00000000 0x0000ff00
 				mmw 0x48001000 0x000000a0 0x000000f0
 				mmw 0x48001008 0x000000f0 0x00000000
 			  }
 			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
 				mmw 0xE0042004 0x000000a0 0x000000c0
 				mmw 0x48001020 0x00000000 0x000fff00
 				mmw 0x48001000 0x000002a0 0x000003f0
 				mmw 0x48001008 0x000003f0 0x00000000
 			  }
 			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
 				mmw 0xE0042004 0x000000e0 0x000000c0
 				mmw 0x48001020 0x00000000 0x0fffff00
 				mmw 0x48001000 0x00002aa0 0x00003ff0
@@ -129,6 +132,7 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
 			  }
 		}
 	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
 		mmw 0xE0042004 0x00000020 0x000000c0
 	}
 }