Georg Acher <acher@in.tum.de> - arm11 wip. run algorithm + small init bugfix.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1023 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
ab362fb528
commit
3b2518bd73
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@ -3,6 +3,8 @@
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* *
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* Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
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* *
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* Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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@ -74,14 +76,14 @@ target_type_t arm11_target =
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ARM11_HANDLER(assert_reset),
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ARM11_HANDLER(deassert_reset),
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ARM11_HANDLER(soft_reset_halt),
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ARM11_HANDLER(get_gdb_reg_list),
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ARM11_HANDLER(read_memory),
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ARM11_HANDLER(write_memory),
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ARM11_HANDLER(bulk_write_memory),
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ARM11_HANDLER(checksum_memory),
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ARM11_HANDLER(add_breakpoint),
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@ -90,7 +92,7 @@ target_type_t arm11_target =
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ARM11_HANDLER(remove_watchpoint),
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ARM11_HANDLER(run_algorithm),
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ARM11_HANDLER(register_commands),
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ARM11_HANDLER(target_create),
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ARM11_HANDLER(init_target),
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@ -408,7 +410,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
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/* this executes JTAG queue: */
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/* this executes JTAG queue: */
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arm11_write_DSCR(arm11, new_dscr);
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@ -427,7 +429,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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/* mcr 15, 0, r0, cr7, cr10, {4} */
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arm11_run_instr_no_data1(arm11, 0xee070f9a);
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u32 dscr = arm11_read_DSCR(arm11);
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LOG_DEBUG("DRAIN, DSCR %08x", dscr);
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@ -621,7 +623,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
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/* restore rDTR */
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if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
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{
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arm11_add_debug_SCAN_N(arm11, 0x05, -1);
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@ -726,7 +728,7 @@ int arm11_halt(struct target_s *target)
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arm11_common_t * arm11 = target->arch_info;
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LOG_DEBUG("target->state: %s",
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LOG_DEBUG("target->state: %s",
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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if (target->state == TARGET_UNKNOWN)
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@ -783,7 +785,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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arm11_common_t * arm11 = target->arch_info;
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LOG_DEBUG("target->state: %s",
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LOG_DEBUG("target->state: %s",
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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@ -821,7 +823,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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/* set all breakpoints */
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size_t brp_num = 0;
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for (bp = target->breakpoints; bp; bp = bp->next)
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{
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arm11_sc7_action_t brp[2];
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@ -832,7 +834,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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brp[1].write = 1;
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brp[1].address = ARM11_SC7_BCR0 + brp_num;
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brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
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arm11_sc7_run(arm11, brp, asizeof(brp));
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LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
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@ -880,7 +882,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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{
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FNC_INFO;
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LOG_DEBUG("target->state: %s",
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LOG_DEBUG("target->state: %s",
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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if (target->state != TARGET_HALTED)
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@ -1016,7 +1018,7 @@ int arm11_deassert_reset(struct target_s *target)
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FNC_INFO;
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#if 0
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LOG_DEBUG("target->state: %s",
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LOG_DEBUG("target->state: %s",
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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@ -1074,7 +1076,7 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
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}
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/* target memory access
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/* target memory access
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* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
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* count: number of items of <size>
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*/
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@ -1283,7 +1285,7 @@ int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
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}
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/* target break-/watchpoint control
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/* target break-/watchpoint control
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* rw: 0 = write, 1 = read, 2 = access
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*/
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int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
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@ -1322,7 +1324,7 @@ int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
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FNC_INFO;
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arm11_common_t * arm11 = target->arch_info;
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arm11->free_brps++;
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return ERROR_OK;
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@ -1342,13 +1344,170 @@ int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
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return ERROR_OK;
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}
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// HACKHACKHACK - FIXME mode/state
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/* target algorithm support */
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int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
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int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
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int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
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int timeout_ms, void *arch_info)
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{
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FNC_INFO_NOTIMPLEMENTED;
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arm11_common_t *arm11 = target->arch_info;
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armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
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// enum armv4_5_state core_state = arm11->core_state;
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// enum armv4_5_mode core_mode = arm11->core_mode;
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u32 context[16];
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u32 cpsr;
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int exit_breakpoint_size = 0;
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int i;
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int retval = ERROR_OK;
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LOG_DEBUG("Running algorithm");
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return ERROR_OK;
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if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
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{
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LOG_ERROR("current target isn't an ARMV4/5 target");
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return ERROR_TARGET_INVALID;
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}
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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// FIXME
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// if (armv4_5_mode_to_number(arm11->core_mode)==-1)
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// return ERROR_FAIL;
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// Save regs
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for (i = 0; i < 16; i++)
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{
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context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
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LOG_DEBUG("Save %i: 0x%x",i,context[i]);
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}
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cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
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LOG_DEBUG("Save CPSR: 0x%x",i,cpsr);
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for (i = 0; i < num_mem_params; i++)
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{
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target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
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}
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// Set register parameters
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for (i = 0; i < num_reg_params; i++)
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{
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reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
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u32 val;
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if (!reg)
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{
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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exit(-1);
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}
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if (reg->size != reg_params[i].size)
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{
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
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exit(-1);
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}
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arm11_set_reg(reg,reg_params[i].value);
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// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
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}
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exit_breakpoint_size = 4;
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/* arm11->core_state = arm11_algorithm_info->core_state;
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if (arm11->core_state == ARMV4_5_STATE_ARM)
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exit_breakpoint_size = 4;
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else if (arm11->core_state == ARMV4_5_STATE_THUMB)
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exit_breakpoint_size = 2;
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else
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{
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LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
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exit(-1);
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}
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*/
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if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
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{
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LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
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buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
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arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
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arm11->reg_list[ARM11_RC_CPSR].valid = 1;
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}
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if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
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{
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LOG_ERROR("can't add breakpoint to finish algorithm execution");
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retval = ERROR_TARGET_FAILURE;
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goto restore;
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}
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target_resume(target, 0, entry_point, 1, 0); // no debug, otherwise breakpoint is not set
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target_wait_state(target, TARGET_HALTED, timeout_ms);
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if (target->state != TARGET_HALTED)
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{
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if ((retval=target_halt(target))!=ERROR_OK)
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return retval;
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if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
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{
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return retval;
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}
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retval = ERROR_TARGET_TIMEOUT;
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goto del_breakpoint;
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}
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if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
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{
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LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
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buf_get_u32(arm11->reg_list[15].value, 0, 32));
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retval = ERROR_TARGET_TIMEOUT;
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goto del_breakpoint;
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}
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for (i = 0; i < num_mem_params; i++)
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{
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if (mem_params[i].direction != PARAM_OUT)
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target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
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}
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for (i = 0; i < num_reg_params; i++)
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{
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if (reg_params[i].direction != PARAM_OUT)
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{
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reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
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if (!reg)
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{
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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exit(-1);
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}
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if (reg->size != reg_params[i].size)
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{
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
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exit(-1);
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}
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buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
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}
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}
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del_breakpoint:
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breakpoint_remove(target, exit_point);
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restore:
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// Restore context
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for (i = 0; i < 16; i++)
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{
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LOG_DEBUG("restoring register %s with value 0x%8.8x",
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arm11->reg_list[i].name, context[i]);
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arm11_set_reg(&arm11->reg_list[i], &context[i]);
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}
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LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
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arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], &cpsr);
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// arm11->core_state = core_state;
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// arm11->core_mode = core_mode;
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return retval;
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}
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int arm11_target_create(struct target_s *target, Jim_Interp *interp)
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@ -1415,7 +1574,7 @@ int arm11_examine(struct target_s *target)
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arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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@ -1464,7 +1623,7 @@ int arm11_examine(struct target_s *target)
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arm11_check_init(arm11, NULL);
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target->type->examined = 1;
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return ERROR_OK;
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}
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@ -1528,7 +1687,7 @@ void arm11_build_reg_cache(target_t *target)
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arm11->reg_list = reg_list;
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/* Build the process context cache */
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/* Build the process context cache */
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cache->name = "arm11 registers";
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cache->next = NULL;
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cache->reg_list = reg_list;
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@ -1537,7 +1696,7 @@ void arm11_build_reg_cache(target_t *target)
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reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
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(*cache_p) = cache;
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// armv7m->core_cache = cache;
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arm11->core_cache = cache;
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// armv7m->process_context = cache;
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size_t i;
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@ -1670,7 +1829,7 @@ arm11_common_t * arm11_find_target(const char * arg)
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{target_t * t;
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for (t = all_targets; t; t = t->next)
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{
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if (t->type != &arm11_target)
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if (strcmp(t->type->name,"arm11"))
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continue;
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arm11_common_t * arm11 = t->arch_info;
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@ -1709,7 +1868,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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return ERROR_TARGET_NOT_HALTED;
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}
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u32 values[6];
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{size_t i;
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@ -1740,8 +1899,8 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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arm11_run_instr_data_prepare(arm11);
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if (read)
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{
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u32 result;
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{
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u32 result;
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arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
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LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
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@ -1752,7 +1911,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
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LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
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values[0], values[1],
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values[0], values[1],
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values[5],
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values[2], values[3], values[4]);
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}
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@ -1,6 +1,8 @@
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/***************************************************************************
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* Copyright (C) 2008 digenius technology GmbH. *
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* *
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* Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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@ -107,6 +109,8 @@ typedef struct arm11_common_s
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size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
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size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
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// GA
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reg_cache_t *core_cache;
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} arm11_common_t;
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