ADIv5: remove ATOMIC/COMPOSITE interface mode
This removes context-sensitivity from the programming interface and makes it possible to know what a block of code does without needing to know the previous history (specifically, the DAP's "trans_mode" setting). The mode was only set to ATOMIC briefly after DAP initialization, making this patch be primarily cleanup; almost everything depends on COMPOSITE. The transactions which shouldn't have been queued were already properly flushing the queue. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
ecff73043c
commit
3b68a708c2
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@ -43,11 +43,16 @@
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* is used to access memory mapped resources and is called a MEM-AP. Also a
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* JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
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*
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* @todo Remove modality (queued/nonqueued, via DAP trans_mode) from all
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* procedure interfaces. Modal programming interfaces are very error prone.
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* Procedures should be either queued, or synchronous. Otherwise input
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* and output constraints are context-sensitive, and it's hard to know
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* what a block of code will do just by reading it.
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* This programming interface allows DAP pipelined operations through a
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* transaction queue. This primarily affects AP operations (such as using
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* a MEM-AP to access memory or registers). If the current transaction has
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* not finished by the time the next one must begin, and the ORUNDETECT bit
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* is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
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* further AP operations will fail. There are two basic methods to avoid
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* such overrun errors. One involves polling for status instead of using
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* transaction piplining. The other involves adding delays to ensure the
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* AP has enough time to complete one operation before starting the next
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* one. (For JTAG these delays are controlled by memaccess_tck.)
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*/
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/*
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@ -67,17 +72,6 @@
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#include "arm_adi_v5.h"
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#include <helper/time_support.h>
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/*
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* Transaction Mode:
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* swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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* Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
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* result checking until swjdp_end_transaction()
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* This must be done before using or deallocating any return variables.
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* swjdp->trans_mode == TRANS_MODE_ATOMIC
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* All reads and writes to the AHB bus are checked for valid completion, and return values
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* are immediatley available.
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*/
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/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
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@ -191,47 +185,32 @@ static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
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/**
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* Utility to write AP registers.
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*/
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static int ap_write_check(struct swjdp_common *dap,
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static inline int ap_write_check(struct swjdp_common *dap,
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uint8_t reg_addr, uint8_t *outvalue)
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{
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adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
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return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
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outvalue, NULL, NULL);
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/* REVISIT except in dap_setup_accessport() almost all call paths
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* set up COMPOSITE. Probably worth just inlining the scan...
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*/
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/* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
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* ack = OK/FAULT and the check CTRL_STAT
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*/
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if (dap->trans_mode == TRANS_MODE_ATOMIC)
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return jtagdp_transaction_endcheck(dap);
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return ERROR_OK;
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}
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static int scan_inout_check_u32(struct swjdp_common *swjdp,
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uint8_t instr, uint8_t reg_addr, uint8_t RnW,
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uint32_t outvalue, uint32_t *invalue)
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{
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int retval;
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/* Issue the read or write */
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adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
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retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
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RnW, outvalue, NULL, NULL);
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if (retval != ERROR_OK)
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return retval;
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/* For reads, collect posted value; RDBUFF has no other effect.
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* Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
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*/
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if ((RnW == DPAP_READ) && (invalue != NULL))
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adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
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retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
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DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
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/* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
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* ack = OK/FAULT and then check CTRL_STAT
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*/
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if ((instr == JTAG_DP_APACC)
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&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
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return jtagdp_transaction_endcheck(swjdp);
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return ERROR_OK;
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return retval;
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}
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int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
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@ -437,17 +416,13 @@ static int dap_ap_write_reg(struct swjdp_common *swjdp,
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}
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/**
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* Write an AP register value.
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* This is synchronous iff the mode is set to ATOMIC, in which
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* case any queued transactions are flushed.
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* Asynchronous (queued) AP register write.
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*
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* @param swjdp The DAP whose currently selected AP will be written.
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* @param reg_addr Eight bit AP register address.
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* @param value Word to be written at reg_addr
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*
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* @return In synchronous mode: ERROR_OK for success, and the register holds
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* the specified value; else a fault code. In asynchronous mode, a status
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* code reflecting whether the transaction was properly queued.
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* @return ERROR_OK if the transaction was properly queued, else a fault code.
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*/
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int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
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uint32_t reg_addr, uint32_t value)
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@ -460,17 +435,13 @@ int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
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}
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/**
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* Read an AP register value.
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* This is synchronous iff the mode is set to ATOMIC, in which
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* case any queued transactions are flushed.
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* Asynchronous (queued) AP register eread.
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*
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* @param swjdp The DAP whose currently selected AP will be read.
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* @param reg_addr Eight bit AP register address.
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* @param value Points to where the 32-bit (little-endian) word will be stored.
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*
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* @return In synchronous mode: ERROR_OK for success, and *value holds
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* the specified value; else a fault code. In asynchronous mode, a status
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* code reflecting whether the transaction was properly queued.
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* @return ERROR_OK if the transaction was properly queued, else a fault code.
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*/
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int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
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uint32_t reg_addr, uint32_t *value)
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@ -486,9 +457,8 @@ int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
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}
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/**
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* Set up transfer parameters for the currently selected MEM-AP.
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* This is synchronous iff the mode is set to ATOMIC, in which
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* case any queued transactions are flushed.
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* Queue transactions setting up transfer parameters for the
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* currently selected MEM-AP.
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*
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* Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
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* initiate data reads or writes using memory or peripheral addresses.
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@ -503,9 +473,7 @@ int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
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* @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
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* matches the cached address, the register is not changed.
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*
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* @return In synchronous mode: ERROR_OK for success, and the AP is set
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* up as requested else a fault code. In asynchronous mode, a status
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* code reflecting whether the transaction was properly queued.
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* @return ERROR_OK if the transaction was properly queued, else a fault code.
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*/
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int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
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{
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@ -550,8 +518,6 @@ int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
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{
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int retval;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* Use banked addressing (REG_BDx) to avoid some link traffic
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* (updating TAR) when reading several consecutive addresses.
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*/
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@ -603,8 +569,6 @@ int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
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{
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int retval;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* Use banked addressing (REG_BDx) to avoid some link traffic
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* (updating TAR) when writing several consecutive addresses.
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*/
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@ -652,8 +616,6 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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uint32_t adr = address;
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uint8_t* pBuffer = buffer;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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count >>= 2;
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wcount = count;
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@ -721,8 +683,6 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
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int retval = ERROR_OK;
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int wcount, blocksize, writecount, i;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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wcount = count >> 1;
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while (wcount > 0)
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@ -799,8 +759,6 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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if (count >= 4)
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return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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while (count > 0)
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{
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dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
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@ -823,8 +781,6 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
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int retval = ERROR_OK;
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int wcount, blocksize, writecount, i;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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wcount = count;
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while (wcount > 0)
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@ -896,8 +852,6 @@ int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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if (count >= 4)
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return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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while (count > 0)
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{
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dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
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@ -925,8 +879,6 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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uint32_t adr = address;
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uint8_t* pBuffer = buffer;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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count >>= 2;
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wcount = count;
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@ -1009,8 +961,6 @@ static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
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int retval = ERROR_OK;
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int wcount, blocksize, readcount, i;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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wcount = count >> 1;
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while (wcount > 0)
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@ -1063,8 +1013,6 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count,
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if (count >= 4)
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return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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while (count > 0)
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{
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dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
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@ -1105,8 +1053,6 @@ static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
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int retval = ERROR_OK;
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int wcount, blocksize, readcount, i;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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wcount = count;
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while (wcount > 0)
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@ -1156,8 +1102,6 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u
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if (count >= 4)
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return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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while (count > 0)
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{
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dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
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@ -1203,7 +1147,6 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
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dap_ap_select(swjdp, 0);
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/* DP initialization */
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swjdp->trans_mode = TRANS_MODE_ATOMIC;
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dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
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dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
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dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
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@ -118,13 +118,6 @@
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#define CSW_MASTER_DEBUG (1 << 29) /* ? */
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#define CSW_DBGSWENABLE (1 << 31)
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/* transaction mode */
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#define TRANS_MODE_NONE 0
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/* Transaction waits for previous to complete */
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#define TRANS_MODE_ATOMIC 1
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/* Freerunning transactions with delays and overrun checking */
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#define TRANS_MODE_COMPOSITE 2
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/**
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* This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
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* A DAP has two types of component: one Debug Port (DP), which is a
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@ -170,9 +163,8 @@ struct swjdp_common
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uint32_t ap_tar_value;
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/* information about current pending SWjDP-AHBAP transaction */
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uint8_t trans_mode;
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uint8_t trans_rw;
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uint8_t ack;
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/**
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* Configures how many extra tck clocks are added after starting a
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* MEM-AP access before we try to read its status (and/or result).
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@ -192,7 +184,7 @@ static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
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/* AP selection applies to future AP transactions */
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void dap_ap_select(struct swjdp_common *dap,uint8_t apsel);
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/* AP transactions ... synchronous given TRANS_MODE_ATOMIC */
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/* Queued AP transactions */
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int dap_setup_accessport(struct swjdp_common *swjdp,
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uint32_t csw, uint32_t tar);
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int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
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@ -70,8 +70,6 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
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mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
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dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
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@ -101,8 +99,6 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
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mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
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dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
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