dsp5680xx - indent fix
no logic changes, only coding style (spaces to tabs, etc) Change-Id: I5933447c633990e103bc62d088ca2e12f11f031d Signed-off-by: rodrigo_l_rosa <rodrigorosa.lg@gmail.com> Reviewed-on: http://openocd.zylin.com/253 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
This commit is contained in:
rodrigo_l_rosa
Øyvind Harboe
parent
b7ce3b5d15
commit
3d0e2547fe
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@ -35,14 +35,10 @@
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#ifndef DSP5680XX_FLASH_H
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#define DSP5680XX_FLASH_H
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#include "imp.h"
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#include <helper/binarybuffer.h>
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#include <helper/time_support.h>
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@ -53,35 +49,39 @@ struct dsp5680xx_flash_bank {
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struct working_area *write_algorithm;
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};
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static int dsp5680xx_build_sector_list(struct flash_bank *bank){
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uint32_t offset = HFM_FLASH_BASE_ADDR;
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bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
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int i;
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for (i = 0; i < bank->num_sectors; ++i){
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bank->sectors[i].offset = i*HFM_SECTOR_SIZE;
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bank->sectors[i].size = HFM_SECTOR_SIZE;
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offset += bank->sectors[i].size;
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = -1;
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}
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LOG_USER("%s not tested yet.",__FUNCTION__);
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return ERROR_OK;
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static int dsp5680xx_build_sector_list(struct flash_bank *bank)
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{
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uint32_t offset = HFM_FLASH_BASE_ADDR;
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bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
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int i;
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for (i = 0; i < bank->num_sectors; ++i) {
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bank->sectors[i].offset = i * HFM_SECTOR_SIZE;
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bank->sectors[i].size = HFM_SECTOR_SIZE;
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offset += bank->sectors[i].size;
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = -1;
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}
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LOG_USER("%s not tested yet.", __func__);
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return ERROR_OK;
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}
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// flash bank dsp5680xx 0 0 0 0 <target#>
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FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command){
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struct dsp5680xx_flash_bank *nbank;
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/* flash bank dsp5680xx 0 0 0 0 <target#> */
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FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command)
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{
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struct dsp5680xx_flash_bank *nbank;
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nbank = malloc(sizeof(struct dsp5680xx_flash_bank));
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nbank = malloc(sizeof(struct dsp5680xx_flash_bank));
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bank->base = HFM_FLASH_BASE_ADDR;
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bank->size = HFM_SIZE_BYTES; // top 4k not accessible
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bank->driver_priv = nbank;
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bank->num_sectors = HFM_SECTOR_COUNT;
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dsp5680xx_build_sector_list(bank);
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bank->base = HFM_FLASH_BASE_ADDR;
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bank->size = HFM_SIZE_BYTES; /* top 4k not accessible */
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bank->driver_priv = nbank;
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bank->num_sectors = HFM_SECTOR_COUNT;
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dsp5680xx_build_sector_list(bank);
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return ERROR_OK;
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return ERROR_OK;
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}
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/**
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@ -93,26 +93,29 @@ FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command){
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*
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* @return
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*/
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static int dsp5680xx_flash_protect_check(struct flash_bank *bank){
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int retval = ERROR_OK;
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uint16_t protected = 0;
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retval = dsp5680xx_f_protect_check(bank->target,&protected);
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if(retval != ERROR_OK){
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for(int i = 0;i<HFM_SECTOR_COUNT;i++)
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bank->sectors[i].is_protected = -1;
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return ERROR_OK;
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}
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for(int i = 0;i<HFM_SECTOR_COUNT/2;i++){
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if(protected & 1){
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bank->sectors[2*i].is_protected = 1;
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bank->sectors[2*i+1].is_protected = 1;
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}else{
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bank->sectors[2*i].is_protected = 0;
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bank->sectors[2*i+1].is_protected = 0;
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}
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protected = (protected >> 1);
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}
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return retval;
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static int dsp5680xx_flash_protect_check(struct flash_bank *bank)
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{
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int retval = ERROR_OK;
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uint16_t protected = 0;
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retval = dsp5680xx_f_protect_check(bank->target, &protected);
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if (retval != ERROR_OK) {
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for (int i = 0; i < HFM_SECTOR_COUNT; i++)
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bank->sectors[i].is_protected = -1;
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return ERROR_OK;
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}
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for (int i = 0; i < HFM_SECTOR_COUNT / 2; i++) {
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if (protected & 1) {
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bank->sectors[2 * i].is_protected = 1;
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bank->sectors[2 * i + 1].is_protected = 1;
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} else {
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bank->sectors[2 * i].is_protected = 0;
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bank->sectors[2 * i + 1].is_protected = 0;
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}
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protected = (protected >> 1);
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}
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return retval;
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}
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/**
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@ -127,21 +130,27 @@ static int dsp5680xx_flash_protect_check(struct flash_bank *bank){
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*
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* @return
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*/
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static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first, int last){
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// This applies security to flash module after next reset, it does not actually apply protection (protection refers to undesired access from the core)
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int retval;
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if(set)
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retval = dsp5680xx_f_lock(bank->target);
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else{
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retval = dsp5680xx_f_unlock(bank->target);
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if (retval == ERROR_OK) {
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/* mark all as erased */
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for (int i = 0; i <= (HFM_SECTOR_COUNT-1); i++)
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/* FM does not recognize it as erased if erased via JTAG. */
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bank->sectors[i].is_erased = 1;
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static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first,
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int last)
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{
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/**
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* This applies security to flash module after next reset, it does
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* not actually apply protection (protection refers to undesired access from the core)
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*/
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int retval;
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if (set)
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retval = dsp5680xx_f_lock(bank->target);
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else {
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retval = dsp5680xx_f_unlock(bank->target);
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if (retval == ERROR_OK) {
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/* mark all as erased */
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for (int i = 0; i <= (HFM_SECTOR_COUNT - 1); i++)
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/* FM does not recognize it as erased if erased via JTAG. */
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bank->sectors[i].is_erased = 1;
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}
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}
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}
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return retval;
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return retval;
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}
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/**
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@ -154,34 +163,54 @@ else{
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*
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* @return
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*/
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static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count){
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int retval;
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if((offset + count/2)>bank->size){
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LOG_ERROR("%s: Flash bank cannot fit data.",__FUNCTION__);
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return ERROR_FAIL;
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}
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if(offset%2){
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LOG_ERROR("%s: Writing to odd addresses not supported. This chip uses word addressing, Openocd only supports byte addressing. The workaround results in disabling writing to odd byte addresses.",__FUNCTION__);
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return ERROR_FAIL;
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}
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retval = dsp5680xx_f_wr(bank->target, buffer, bank->base + offset/2, count, 0);
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uint32_t addr_word;
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for(addr_word = bank->base + offset/2;addr_word<count/2;addr_word+=(HFM_SECTOR_SIZE/2)){
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if(retval == ERROR_OK)
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bank->sectors[addr_word/(HFM_SECTOR_SIZE/2)].is_erased = 0;
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else
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bank->sectors[addr_word/(HFM_SECTOR_SIZE/2)].is_erased = -1;
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}
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return retval;
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static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t * buffer,
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uint32_t offset, uint32_t count)
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{
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int retval;
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if ((offset + count / 2) > bank->size) {
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LOG_ERROR("%s: Flash bank cannot fit data.", __func__);
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return ERROR_FAIL;
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}
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if (offset % 2) {
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/**
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* Writing to odd addresses not supported.
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* This chip uses word addressing, Openocd only supports byte addressing.
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* The workaround results in disabling writing to odd byte addresses
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*/
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LOG_ERROR
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("%s: Writing to odd addresses not supported for this target",
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__func__);
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return ERROR_FAIL;
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}
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retval =
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dsp5680xx_f_wr(bank->target, buffer, bank->base + offset / 2, count,
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0);
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uint32_t addr_word;
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for (addr_word = bank->base + offset / 2; addr_word < count / 2;
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addr_word += (HFM_SECTOR_SIZE / 2)) {
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if (retval == ERROR_OK)
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bank->sectors[addr_word /
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(HFM_SECTOR_SIZE / 2)].is_erased = 0;
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else
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bank->sectors[addr_word /
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(HFM_SECTOR_SIZE / 2)].is_erased = -1;
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}
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return retval;
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}
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static int dsp5680xx_probe(struct flash_bank *bank){
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LOG_DEBUG("%s not implemented",__FUNCTION__);
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return ERROR_OK;
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static int dsp5680xx_probe(struct flash_bank *bank)
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{
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LOG_DEBUG("%s not implemented", __func__);
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return ERROR_OK;
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}
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static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf, int buf_size){
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snprintf(buf, buf_size, "\ndsp5680xx flash driver info:\n - Currently only full erase/lock/unlock are implemented. \n - Call with bank==0 and sector 0 to 0.\n - Protect requires arp_init-reset to complete. \n - Before removing protection the master tap must be selected, and arp_init-reset is required to complete unlocking.");
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static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf,
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int buf_size)
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{
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snprintf(buf, buf_size,
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"\ndsp5680xx flash driver info:\n - See comments in code.");
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return ERROR_OK;
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}
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@ -195,19 +224,26 @@ static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf, int buf_size
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*
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* @return
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*/
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static int dsp5680xx_flash_erase(struct flash_bank * bank, int first, int last){
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int retval;
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retval = dsp5680xx_f_erase(bank->target, (uint32_t) first, (uint32_t) last);
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if ((!(first|last)) || ((first == 0) && (last == (HFM_SECTOR_COUNT-1))))
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last = HFM_SECTOR_COUNT-1;
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if(retval == ERROR_OK)
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for(int i = first;i<=last;i++)
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bank->sectors[i].is_erased = 1;
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else
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// If an error occurred unknown status is set even though some sector could have been correctly erased.
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for(int i = first;i<=last;i++)
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bank->sectors[i].is_erased = -1;
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return retval;
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static int dsp5680xx_flash_erase(struct flash_bank *bank, int first, int last)
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{
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int retval;
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retval =
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dsp5680xx_f_erase(bank->target, (uint32_t) first, (uint32_t) last);
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if ((!(first | last))
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|| ((first == 0) && (last == (HFM_SECTOR_COUNT - 1))))
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last = HFM_SECTOR_COUNT - 1;
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if (retval == ERROR_OK)
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for (int i = first; i <= last; i++)
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bank->sectors[i].is_erased = 1;
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else
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/**
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* If an error occurred unknown status
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*is set even though some sector could have been correctly erased.
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*/
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for (int i = first; i <= last; i++)
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bank->sectors[i].is_erased = -1;
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return retval;
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}
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/**
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@ -218,37 +254,41 @@ if ((!(first|last)) || ((first == 0) && (last == (HFM_SECTOR_COUNT-1))))
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*
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* @return
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*/
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static int dsp5680xx_flash_erase_check(struct flash_bank * bank){
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int retval = ERROR_OK;
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uint8_t erased = 0;
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uint32_t i;
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for(i=0;i<HFM_SECTOR_COUNT;i++){
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if(bank->sectors[i].is_erased == -1){
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retval = dsp5680xx_f_erase_check(bank->target,&erased,i);
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if (retval != ERROR_OK){
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bank->sectors[i].is_erased = -1;
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}else{
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if(erased)
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bank->sectors[i].is_erased = 1;
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else
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bank->sectors[i].is_erased = 0;
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}
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}
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}
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return retval;
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static int dsp5680xx_flash_erase_check(struct flash_bank *bank)
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{
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int retval = ERROR_OK;
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uint8_t erased = 0;
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uint32_t i;
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for (i = 0; i < HFM_SECTOR_COUNT; i++) {
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if (bank->sectors[i].is_erased == -1) {
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retval =
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dsp5680xx_f_erase_check(bank->target, &erased, i);
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if (retval != ERROR_OK) {
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bank->sectors[i].is_erased = -1;
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} else {
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if (erased)
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bank->sectors[i].is_erased = 1;
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else
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bank->sectors[i].is_erased = 0;
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}
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}
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}
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return retval;
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}
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struct flash_driver dsp5680xx_flash = {
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.name = "dsp5680xx_flash",
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.flash_bank_command = dsp5680xx_flash_bank_command,
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.erase = dsp5680xx_flash_erase,
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.protect = dsp5680xx_flash_protect,
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.write = dsp5680xx_flash_write,
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//.read = default_flash_read,
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.probe = dsp5680xx_probe,
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.auto_probe = dsp5680xx_probe,
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.erase_check = dsp5680xx_flash_erase_check,
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.protect_check = dsp5680xx_flash_protect_check,
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.info = dsp5680xx_flash_info
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.name = "dsp5680xx_flash",
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.flash_bank_command = dsp5680xx_flash_bank_command,
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.erase = dsp5680xx_flash_erase,
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.protect = dsp5680xx_flash_protect,
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.write = dsp5680xx_flash_write,
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/* .read = default_flash_read, */
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.probe = dsp5680xx_probe,
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.auto_probe = dsp5680xx_probe,
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.erase_check = dsp5680xx_flash_erase_check,
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.protect_check = dsp5680xx_flash_protect_check,
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.info = dsp5680xx_flash_info
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};
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#endif // dsp5680xx_flash.h
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File diff suppressed because it is too large
Load Diff
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@ -37,140 +37,164 @@
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*
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*/
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#define S_FILE_DATA_OFFSET 0x200000
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#define TIME_DIV_FREESCALE 0.3
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//----------------------------------------------------------------
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// JTAG
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* JTAG
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*----------------------------------------------------------------
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*/
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#define DSP5680XX_JTAG_CORE_TAP_IRLEN 4
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#define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8
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#define JTAG_STATUS_MASK 0x0F
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#define JTAG_STATUS_MASK 0x0F
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#define JTAG_STATUS_NORMAL 0x01
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#define JTAG_STATUS_STOPWAIT 0x05
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#define JTAG_STATUS_BUSY 0x09
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#define JTAG_STATUS_DEBUG 0x0D
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#define JTAG_STATUS_DEAD 0x0f
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#define JTAG_STATUS_DEAD 0x0f
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#define JTAG_INSTR_EXTEST 0x0
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#define JTAG_INSTR_SAMPLE_PRELOAD 0x1
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#define JTAG_INSTR_IDCODE 0x2
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#define JTAG_INSTR_EXTEST_PULLUP 0x3
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#define JTAG_INSTR_HIGHZ 0x4
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#define JTAG_INSTR_EXTEST_PULLUP 0x3
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#define JTAG_INSTR_HIGHZ 0x4
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#define JTAG_INSTR_CLAMP 0x5
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#define JTAG_INSTR_ENABLE_ONCE 0x6
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#define JTAG_INSTR_DEBUG_REQUEST 0x7
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#define JTAG_INSTR_BYPASS 0xF
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// Master TAP instructions from MC56F8000RM.pdf
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* Master TAP instructions from MC56F8000RM.pdf
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* ----------------------------------------------------------------
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*/
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#define MASTER_TAP_CMD_BYPASS 0xF
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#define MASTER_TAP_CMD_IDCODE 0x2
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#define MASTER_TAP_CMD_TLM_SEL 0x5
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#define MASTER_TAP_CMD_FLASH_ERASE 0x8
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// EOnCE control register info
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* EOnCE control register info
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_OCR_EX (1<<5)
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/* EX Bit Definition
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0 Remain in the Debug Processing State
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1 Leave the Debug Processing State */
|
||||
0 Remain in the Debug Processing State
|
||||
1 Leave the Debug Processing State */
|
||||
#define DSP5680XX_ONCE_OCR_GO (1<<6)
|
||||
/* GO Bit Definition
|
||||
0 Inactive—No Action Taken
|
||||
1 Execute Controller Instruction */
|
||||
0 Inactive—No Action Taken
|
||||
1 Execute Controller Instruction */
|
||||
#define DSP5680XX_ONCE_OCR_RW (1<<7)
|
||||
/* RW Bit Definition
|
||||
0 Write To the Register Specified by the RS[4:0] Bits
|
||||
1 ReadFrom the Register Specified by the RS[4:0] Bits */
|
||||
//----------------------------------------------------------------
|
||||
/** RW Bit Definition
|
||||
* 0 Write To the Register Specified by the RS[4:0] Bits
|
||||
* 1 ReadFrom the Register Specified by the RS[4:0] Bits
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// EOnCE Status Register
|
||||
//----------------------------------------------------------------
|
||||
#define DSP5680XX_ONCE_OSCR_OS1 (1<<5)
|
||||
#define DSP5680XX_ONCE_OSCR_OS0 (1<<4)
|
||||
//----------------------------------------------------------------
|
||||
/** ----------------------------------------------------------------
|
||||
* EOnCE Status Register
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define DSP5680XX_ONCE_OSCR_OS1 (1<<5)
|
||||
#define DSP5680XX_ONCE_OSCR_OS0 (1<<4)
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// EOnCE Core Status - Describes the operating status of the core controller
|
||||
//----------------------------------------------------------------
|
||||
/** ----------------------------------------------------------------
|
||||
* EOnCE Core Status - Describes the operating status of the core controller
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define DSP5680XX_ONCE_OSCR_NORMAL_M (0)
|
||||
//00 - Normal - Controller Core Executing Instructions or in Reset
|
||||
/* 00 - Normal - Controller Core Executing Instructions or in Reset */
|
||||
#define DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0)
|
||||
//01 - Stop/Wait - Controller Core in Stop or Wait Mode
|
||||
/* 01 - Stop/Wait - Controller Core in Stop or Wait Mode */
|
||||
#define DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1)
|
||||
//10 - Busy - Controller is Performing External or Peripheral Access (Wait States)
|
||||
/* 10 - Busy - Controller is Performing External or Peripheral Access (Wait States) */
|
||||
#define DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)
|
||||
//11 - Debug - Controller Core Halted and in Debug Mode
|
||||
/* 11 - Debug - Controller Core Halted and in Debug Mode */
|
||||
#define EONCE_STAT_MASK 0x30
|
||||
//----------------------------------------------------------------
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
|
||||
//----------------------------------------------------------------
|
||||
#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
|
||||
#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
|
||||
#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
|
||||
#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */
|
||||
#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */
|
||||
#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */
|
||||
#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */
|
||||
#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */
|
||||
#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
|
||||
#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
|
||||
#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
|
||||
#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
|
||||
#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
|
||||
#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
|
||||
#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
|
||||
#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
|
||||
#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
|
||||
#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
|
||||
#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
|
||||
//----------------------------------------------------------------
|
||||
/** ----------------------------------------------------------------
|
||||
* Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
|
||||
#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
|
||||
#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
|
||||
#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */
|
||||
#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */
|
||||
#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */
|
||||
#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */
|
||||
#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */
|
||||
#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
|
||||
#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
|
||||
#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
|
||||
#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
|
||||
#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
|
||||
#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
|
||||
#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
|
||||
#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
|
||||
#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
|
||||
#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
|
||||
#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define FLUSH_COUNT_READ_WRITE 8192 // This value works, higher values (and lower...) may work as well.
|
||||
#define FLUSH_COUNT_FLASH 8192
|
||||
//----------------------------------------------------------------
|
||||
// HFM (flash module) Commands (ref:MC56F801xRM.pdf@159)
|
||||
//----------------------------------------------------------------
|
||||
#define HFM_ERASE_VERIFY 0x05
|
||||
/** ----------------------------------------------------------------
|
||||
* HFM (flash module) Commands (ref:MC56F801xRM.pdf@159)
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define HFM_ERASE_VERIFY 0x05
|
||||
#define HFM_CALCULATE_DATA_SIGNATURE 0x06
|
||||
#define HFM_WORD_PROGRAM 0x20
|
||||
#define HFM_PAGE_ERASE 0x40
|
||||
#define HFM_MASS_ERASE 0x41
|
||||
#define HFM_WORD_PROGRAM 0x20
|
||||
#define HFM_PAGE_ERASE 0x40
|
||||
#define HFM_MASS_ERASE 0x41
|
||||
#define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66
|
||||
//----------------------------------------------------------------
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Flashing (ref:MC56F801xRM.pdf@159)
|
||||
//----------------------------------------------------------------
|
||||
#define HFM_BASE_ADDR 0x0F400 // In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR to get data into x: mem.)
|
||||
// The following are register addresses, not memory addresses (though all registers are memory mapped)
|
||||
#define HFM_CLK_DIV 0x00 // r/w
|
||||
#define HFM_CNFG 0x01 // r/w
|
||||
#define HFM_SECHI 0x03 // r
|
||||
#define HFM_SECLO 0x04 // r
|
||||
#define HFM_PROT 0x10 // r/w
|
||||
#define HFM_PROTB 0x11 // r/w
|
||||
#define HFM_USTAT 0x13 // r/w
|
||||
#define HFM_CMD 0x14 // r/w
|
||||
#define HFM_DATA 0x18 // r
|
||||
#define HFM_OPT1 0x1B // r
|
||||
#define HFM_TSTSIG 0x1D // r
|
||||
/** ----------------------------------------------------------------
|
||||
* Flashing (ref:MC56F801xRM.pdf@159)
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define HFM_BASE_ADDR 0x0F400 /** In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR
|
||||
* to get data into x: mem.)
|
||||
*/
|
||||
/**
|
||||
* The following are register addresses, not memory
|
||||
* addresses (though all registers are memory mapped)
|
||||
*/
|
||||
#define HFM_CLK_DIV 0x00 /* r/w */
|
||||
#define HFM_CNFG 0x01 /* r/w */
|
||||
#define HFM_SECHI 0x03 /* r */
|
||||
#define HFM_SECLO 0x04 /* r */
|
||||
#define HFM_PROT 0x10 /* r/w */
|
||||
#define HFM_PROTB 0x11 /* r/w */
|
||||
#define HFM_USTAT 0x13 /* r/w */
|
||||
#define HFM_CMD 0x14 /* r/w */
|
||||
#define HFM_DATA 0x18 /* r */
|
||||
#define HFM_OPT1 0x1B /* r */
|
||||
#define HFM_TSTSIG 0x1D /* r */
|
||||
|
||||
#define HFM_EXEC_COMPLETE 0x40
|
||||
|
||||
// User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5)
|
||||
/* User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5) */
|
||||
#define HFM_USTAT_MASK_BLANK 0x4
|
||||
#define HFM_USTAT_MASK_PVIOL_ACCER 0x30
|
||||
|
||||
|
|
@ -182,11 +206,11 @@
|
|||
#define HFM_CLK_DEFAULT 0x27
|
||||
/* 0x27 according to freescale cfg, but 0x40 according to freescale spreadsheet... */
|
||||
#define HFM_FLASH_BASE_ADDR 0x0
|
||||
#define HFM_SIZE_BYTES 0x4000 // bytes
|
||||
#define HFM_SIZE_WORDS 0x2000 // words
|
||||
#define HFM_SECTOR_SIZE 0x200 // Size in bytes
|
||||
#define HFM_SIZE_BYTES 0x4000 /* bytes */
|
||||
#define HFM_SIZE_WORDS 0x2000 /* words */
|
||||
#define HFM_SECTOR_SIZE 0x200 /* Size in bytes */
|
||||
#define HFM_SECTOR_COUNT 0x20
|
||||
// A 16K block in pages of 256 words.
|
||||
/* A 16K block in pages of 256 words. */
|
||||
|
||||
/**
|
||||
* Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.
|
||||
|
|
@ -194,26 +218,34 @@
|
|||
#define HFM_LOCK_FLASH 0xE70A
|
||||
#define HFM_LOCK_ADDR_L 0x1FF7
|
||||
#define HFM_LOCK_ADDR_H 0x1FF8
|
||||
//----------------------------------------------------------------
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Register Memory Map (eonce_rev.1.0_0208081.pdf@16)
|
||||
//----------------------------------------------------------------
|
||||
/** ----------------------------------------------------------------
|
||||
* Register Memory Map (eonce_rev.1.0_0208081.pdf@16)
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define MC568013_EONCE_OBASE_ADDR 0xFF
|
||||
// The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...)
|
||||
#define MC568013_EONCE_TX_RX_ADDR 0xFFFE //
|
||||
#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR
|
||||
#define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR
|
||||
//----------------------------------------------------------------
|
||||
/* The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) */
|
||||
#define MC568013_EONCE_TX_RX_ADDR 0xFFFE
|
||||
#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF /* Relative to EONCE_OBASE_ADDR */
|
||||
#define MC568013_EONCE_OCR 0xFFA0 /* Relative to EONCE_OBASE_ADDR */
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// SIM addresses & commands (MC56F80xx.h from freescale)
|
||||
//----------------------------------------------------------------
|
||||
/** ----------------------------------------------------------------
|
||||
* SIM addresses & commands (MC56F80xx.h from freescale)
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define MC568013_SIM_BASE_ADDR 0xF140
|
||||
#define MC56803x_2x_SIM_BASE_ADDR 0xF100
|
||||
|
||||
#define SIM_CMD_RESET 0x10
|
||||
//----------------------------------------------------------------
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
|
|
@ -253,17 +285,18 @@
|
|||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
struct dsp5680xx_common{
|
||||
//TODO
|
||||
uint32_t stored_pc;
|
||||
int flush;
|
||||
bool debug_mode_enabled;
|
||||
struct dsp5680xx_common {
|
||||
uint32_t stored_pc;
|
||||
int flush;
|
||||
bool debug_mode_enabled;
|
||||
};
|
||||
|
||||
extern struct dsp5680xx_common dsp5680xx_context;
|
||||
|
||||
static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target){
|
||||
return target->arch_info;
|
||||
static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target
|
||||
*target)
|
||||
{
|
||||
return target->arch_info;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -279,7 +312,8 @@ static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock);
|
||||
int dsp5680xx_f_wr(struct target *target, uint8_t * buffer, uint32_t address,
|
||||
uint32_t count, int is_flash_lock);
|
||||
|
||||
/**
|
||||
* The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis.
|
||||
|
|
@ -290,7 +324,8 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased, uint32_t sector);
|
||||
int dsp5680xx_f_erase_check(struct target *target, uint8_t * erased,
|
||||
uint32_t sector);
|
||||
|
||||
/**
|
||||
* Erases either a sector or the complete flash array. If either the range first-last covers the complete array or if @first == 0 and @last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased.
|
||||
|
|
@ -301,7 +336,7 @@ int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased, uint32_t se
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_erase(struct target * target, int first, int last);
|
||||
int dsp5680xx_f_erase(struct target *target, int first, int last);
|
||||
|
||||
/**
|
||||
* Reads the memory mapped protection register. A 1 implies the sector is protected, a 0 implies the sector is not protected.
|
||||
|
|
@ -311,7 +346,7 @@ int dsp5680xx_f_erase(struct target * target, int first, int last);
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected);
|
||||
int dsp5680xx_f_protect_check(struct target *target, uint16_t * protected);
|
||||
|
||||
/**
|
||||
* Writes the flash security words with a specific value. The chip's security will be enabled after the first reset following the execution of this function.
|
||||
|
|
@ -320,7 +355,7 @@ int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected);
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_lock(struct target * target);
|
||||
int dsp5680xx_f_lock(struct target *target);
|
||||
|
||||
/**
|
||||
* Executes a mass erase command. The must be done from the Master tap.
|
||||
|
|
@ -331,6 +366,6 @@ int dsp5680xx_f_lock(struct target * target);
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_unlock(struct target * target);
|
||||
int dsp5680xx_f_unlock(struct target *target);
|
||||
|
||||
#endif // dsp5680xx.h
|
||||
#endif /* dsp5680xx.h */
|
||||
|
|
|
|||
Loading…
Reference in New Issue