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ARM: rename armv4_5_build_reg_cache() as arm_*()

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Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-12-04 20:33:02 -08:00
parent c2cc677056
commit 3edcff8b8e
6 changed files with 10 additions and 11 deletions
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2
src/target/arm7tdmi.c
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@ -643,7 +643,7 @@ static void arm7tdmi_build_reg_cache(struct target *target)
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_arm(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
(*cache_p) = arm_build_reg_cache(target, armv4_5);
}
int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)

2
src/target/arm9tdmi.c
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@ -753,7 +753,7 @@ static void arm9tdmi_build_reg_cache(struct target *target)
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_arm(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
(*cache_p) = arm_build_reg_cache(target, armv4_5);
}
int arm9tdmi_init_target(struct command_context *cmd_ctx,

2
src/target/arm_dpm.c
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@ -819,7 +819,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
arm->read_core_reg = arm_dpm_read_core_reg;
arm->write_core_reg = arm_dpm_write_core_reg;
cache = armv4_5_build_reg_cache(target, arm);
cache = arm_build_reg_cache(target, arm);
if (!cache)
return ERROR_FAIL;

10
src/target/armv4_5.c
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@ -533,7 +533,7 @@ static const struct reg_arch_type arm_reg_type = {
.set = armv4_5_set_core_reg,
};
struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
@ -557,7 +557,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
{
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
&& armv4_5_common->core_type != ARM_MODE_MON)
&& arm->core_type != ARM_MODE_MON)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
@ -565,7 +565,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
arch_info[i].num = arm_core_regs[i].cookie;
arch_info[i].mode = arm_core_regs[i].mode;
arch_info[i].target = target;
arch_info[i].armv4_5_common = armv4_5_common;
arch_info[i].armv4_5_common = arm;
reg_list[i].name = (char *) arm_core_regs[i].name;
reg_list[i].size = 32;
@ -576,8 +576,8 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
cache->num_regs++;
}
armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
armv4_5_common->core_cache = cache;
arm->cpsr = reg_list + ARMV4_5_CPSR;
arm->core_cache = cache;
return cache;
}

3
src/target/armv4_5.h
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@ -177,8 +177,7 @@ struct arm_reg
uint32_t value;
};
struct reg_cache* armv4_5_build_reg_cache(struct target *target,
struct arm *armv4_5_common);
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
int armv4_5_arch_state(struct target *target);
int armv4_5_get_gdb_reg_list(struct target *target,

2
src/target/xscale.c
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@ -2859,7 +2859,7 @@ static void xscale_build_reg_cache(struct target *target)
int i;
int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
(*cache_p) = arm_build_reg_cache(target, armv4_5);
(*cache_p)->next = malloc(sizeof(struct reg_cache));
cache_p = &(*cache_p)->next;