atm920t : fix breakpoints and data cache handling
Breakpoints did not work because the data cache was not flushed properly. As a bonus add capability to write to memory marked as read only by the MMU, which allows software breakpoints in such memory regions.
This commit is contained in:
Marc Pignat
Øyvind Harboe
parent
aa8db989b9
commit
3f30563c88
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@ -559,34 +559,120 @@ static int arm920t_write_phys_memory(struct target *target,
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/** Writes a buffer, in the specified word size, with current MMU settings. */
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int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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int arm920t_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */
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struct arm920t_common *arm920t = target_to_arm920(target);
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if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
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return retval;
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/* This fn is used to write breakpoints, so we need to make sure
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* that the data cache is flushed and the instruction cache is
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* invalidated
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*/
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if (((size == 4) || (size == 2)) && (count == 1))
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/* FIX!!!! this should be cleaned up and made much more general. The
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* plan is to write up and test on arm920t specifically and
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* then generalize and clean up afterwards. */
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if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
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{
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struct arm920t_common *arm920t = target_to_arm920(target);
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/* special case the handling of single word writes to bypass MMU
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* to allow implementation of breakpoints in memory marked read only
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* by MMU */
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int type;
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uint32_t cb;
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int domain;
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uint32_t ap;
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uint32_t pa;
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/*
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* We need physical address and cb
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*/
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pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
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if (type == -1)
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{
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return pa;
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}
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if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
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{
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LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
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/* MCR p15,0,Rd,c7,c10,2 */
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retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
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if (cb & 0x1)
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{
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LOG_DEBUG("D-Cache buffered, drain write buffer");
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/*
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* Buffered ?
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* Drain write buffer - MCR p15,0,Rd,c7,c10,4
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*/
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retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 10, 4), 0x0, 0);
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if (retval != ERROR_OK)
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return retval;
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}
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if (cb == 0x3)
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{
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/*
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* Write back memory ? -> clean cache
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*
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* There is no way for cleaning a data cache line using
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* cp15 scan chain, so copy the full cache line from
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* cache to physical memory.
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*/
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uint8_t data[32];
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LOG_DEBUG("D-Cache in 'write back' mode, flush cache line");
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retval = target_read_memory(target, address & cache_mask, 1, sizeof(data), &data[0]);
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if (retval != ERROR_OK)
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return retval;
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retval = armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa & cache_mask, 1, sizeof(data), &data[0]);
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if (retval != ERROR_OK)
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return retval;
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}
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/* Cached ? */
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if (cb & 0x2)
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{
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/*
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* Cached ? -> Invalidate data cache using MVA
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*
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* MCR p15,0,Rd,c7,c6,1
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*/
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LOG_DEBUG("D-Cache enabled, invalidate cache line");
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retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0, address & cache_mask);
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if (retval != ERROR_OK)
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return retval;
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}
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}
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/* write directly to physical memory bypassing any read only MMU bits, etc. */
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retval = armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
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if (retval != ERROR_OK)
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return retval;
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} else
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{
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if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
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return retval;
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}
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/* If ICache is enabled, we have to invalidate affected ICache lines
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* the DCache is forced to write-through, so we don't have to clean it here
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*/
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if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
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{
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if (count <= 1)
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{
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/* invalidate ICache single entry with MVA
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* ee070f35 mcr 15, 0, r0, cr7, cr5, {1}
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*/
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LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
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retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 1), 0x0, address & cache_mask);
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if (retval != ERROR_OK)
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return retval;
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}
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if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
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else
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{
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LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
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retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
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/* invalidate ICache
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* 8: ee070f15 mcr 15, 0, r0, cr7, cr5, {0}
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* */
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retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0x0, 0x0);
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if (retval != ERROR_OK)
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return retval;
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}
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