tcl/target: Add K3 basic support
Add basic connection details for AM654 and J721E SoCs from TI. See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: https://www.ti.com/lit/pdf/spruid7 See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: https://www.ti.com/lit/pdf/spruil1 See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Change-Id: Ie5108c6ad6f1304a6bf5b9f81aa9ebd33b8a559d Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: http://openocd.zylin.com/5182 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
This commit is contained in:
Nishanth Menon
Antonio Borneo
parent
4307d93eb0
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431dd88536
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
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#
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# Texas Instruments K3 devices:
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# * AM654x: https://www.ti.com/lit/pdf/spruid7
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# Has 4 ARMV8 Cores and 2 R5 Cores and an M3
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# * J721E: https://www.ti.com/lit/pdf/spruil1
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# Has 2 ARMV8 Cores and 6 R5 Cores and an M3
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# * J7200: https://www.ti.com/lit/pdf/spruiu1
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# Has 2 ARMV8 Cores and 4 R5 Cores and an M3
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# * AM642: https://www.ti.com/lit/pdf/spruim2
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# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
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#
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if { [info exists SOC] } {
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set _soc $SOC
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} else {
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set _soc am654
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}
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# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
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if { [info exists V8_SMP_DEBUG] } {
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set _v8_smp_debug $V8_SMP_DEBUG
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} else {
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set _v8_smp_debug 0
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}
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# Common Definitions
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# CM3 the very first processor - all current SoCs have it.
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set CM3_CTIBASE {0x3C016000}
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# M3 power-ap unlock offsets
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set _m3_ap_unlock_offsets {0xf0 0x44}
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# All the ARMV8s are the next processors.
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# CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
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set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
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set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
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# And we add up the R5s
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# (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
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set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
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set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
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# Finally an M4F
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set CM4_CTIBASE {0x20001000}
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# M4 may be present on some very few SoCs
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set _mcu_m4_cores 0
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# M4 power-ap unlock offsets
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set _m4_ap_unlock_offsets {0xf0 0x60}
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# Set configuration overrides for each SOC
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switch $_soc {
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am654 {
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set _CHIPNAME am654
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set _K3_DAP_TAPID 0x0bb5a02f
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# AM654 has 2 clusters of 2 A53 cores each.
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set _armv8_cpu_name a53
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set _armv8_cores 4
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# AM654 has 1 cluster of 2 R5s cores.
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set _r5_cores 2
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set _mcu_r5_cores 2
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set _mcu_base_core_id 0
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set _main0_r5_cores 0
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set _main0_base_core_id 0
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set _main1_r5_cores 0
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set _main1_base_core_id 0
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# M3 power-ap unlock offsets
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set _m3_ap_unlock_offsets {0xf0 0x50}
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}
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am642 {
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set _CHIPNAME am642
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set _K3_DAP_TAPID 0x0bb3802f
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# AM642 has 1 clusters of 2 A53 cores each.
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set _armv8_cpu_name a53
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set _armv8_cores 2
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set ARMV8_DBGBASE {0x90010000 0x90110000}
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set ARMV8_CTIBASE {0x90020000 0x90120000}
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# AM642 has 2 cluster of 2 R5s cores.
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set _r5_cores 4
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set _mcu_r5_cores 0
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set _mcu_base_core_id 0
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set _main0_r5_cores 2
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set _main0_base_core_id 0
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set _main1_r5_cores 2
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set _main1_base_core_id 2
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set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
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set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
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# M4 processor
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set _mcu_m4_cores 1
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}
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j721e {
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set _CHIPNAME j721e
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set _K3_DAP_TAPID 0x0bb6402f
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# J721E has 1 cluster of 2 A72 cores.
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set _armv8_cpu_name a72
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set _armv8_cores 2
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# J721E has 3 clusters of 2 R5 cores each.
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set _r5_cores 6
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set _mcu_r5_cores 2
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set _mcu_base_core_id 0
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set _main0_r5_cores 2
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set _main0_base_core_id 2
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set _main1_r5_cores 2
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set _main1_base_core_id 4
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}
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j7200 {
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set _CHIPNAME j7200
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set _K3_DAP_TAPID 0x0bb6d02f
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# J7200 has 1 cluster of 2 A72 cores.
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set _armv8_cpu_name a72
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set _armv8_cores 2
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# J7200 has 2 clusters of 2 R5 cores each.
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set _r5_cores 4
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set _mcu_r5_cores 2
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set _mcu_base_core_id 0
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set _main0_r5_cores 2
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set _main0_base_core_id 2
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set _main1_r5_cores 0
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set _main1_base_core_id 0
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set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
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set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
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# M3 CTI base
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set CM3_CTIBASE {0x20001000}
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}
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default {
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echo "'$_soc' is invalid!"
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}
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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set _CTINAME $_CHIPNAME.cti
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# M3 is always present
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cti create $_CTINAME.m3 -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
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target create $_TARGETNAME.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
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$_TARGETNAME.m3 configure -event reset-assert { }
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proc m3_up { args } {
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# To access M3, we need to enable the JTAG access for the same.
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# Ensure Power-AP unlocked
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$::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 0] 0x00190000
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$::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 1] 0x00102098
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$::_TARGETNAME.m3 arp_examine
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}
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set _v8_smp_targets ""
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for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
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cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
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-baseaddr [lindex $ARMV8_CTIBASE $_core]
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target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
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-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
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set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
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}
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# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
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set _armv8_up_cmd "$_armv8_cpu_name"_up
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# Available if V8_SMP_DEBUG is set to non-zero value
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set _armv8_smp_cmd "$_armv8_cpu_name"_smp
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if { $_v8_smp_debug == 0 } {
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proc $_armv8_up_cmd { args } {
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foreach { _core } [set args] {
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$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
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$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
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}
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}
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} else {
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proc $_armv8_smp_cmd { args } {
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for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
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$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
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$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
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$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
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}
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# Set Default target are core 0
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targets $::_TARGETNAME.$::_armv8_cpu_name.0
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}
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# Declare SMP
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target smp $:::_v8_smp_targets
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}
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for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
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cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
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-baseaddr [lindex $R5_CTIBASE $_core]
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# inactive core examination will fail - wait till startup of additional core
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target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
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-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
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}
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if { $_mcu_r5_cores != 0 } {
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proc mcu_r5_up { args } {
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foreach { _core } [set args] {
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set _core [expr {$_core + $::_mcu_base_core_id}]
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$::_TARGETNAME.r5.$_core arp_examine
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$::_TARGETNAME.r5.$_core cortex_r4 dbginit
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}
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}
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}
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if { $_main0_r5_cores != 0 } {
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proc main0_r5_up { args } {
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foreach { _core } [set args] {
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set _core [expr {$_core + $::_main0_base_core_id}]
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$::_TARGETNAME.r5.$_core arp_examine
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$::_TARGETNAME.r5.$_core cortex_r4 dbginit
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}
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}
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}
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if { $_main1_r5_cores != 0 } {
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proc main1_r5_up { args } {
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foreach { _core } [set args] {
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set _core [expr {$_core + $::_main1_base_core_id}]
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$::_TARGETNAME.r5.$_core arp_examine
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$::_TARGETNAME.r5.$_core cortex_r4 dbginit
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}
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}
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}
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if { $_mcu_m4_cores != 0 } {
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cti create $_CTINAME.m4 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
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target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
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$_TARGETNAME.m4 configure -event reset-assert { }
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proc m4_up { args } {
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# To access M4, we need to enable the JTAG access for the same.
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# Ensure Power-AP unlocked
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$::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000
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$::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 1] 0x00102098
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$::_TARGETNAME.m4 arp_examine
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}
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}
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