diff --git a/tcl/target/cc2538.cfg b/tcl/target/cc2538.cfg
new file mode 100755
index 000000000..81593c105
--- /dev/null
+++ b/tcl/target/cc2538.cfg
@@ -0,0 +1,16 @@
+# Config for Texas Instruments low power RF SoC CC2538
+# http://www.ti.com/lit/pdf/swru319
+
+if { [info exists CHIPNAME] } {
+   set CHIPNAME $CHIPNAME
+} else {
+   set CHIPNAME cc2538
+}
+
+if { [info exists JRC_TAPID] } {
+   set JRC_TAPID $JRC_TAPID
+} else {
+   set JRC_TAPID 0x8B96402F
+}
+
+source [find target/cc26xx.cfg]
diff --git a/tcl/target/cc26xx.cfg b/tcl/target/cc26xx.cfg
new file mode 100755
index 000000000..0fa460035
--- /dev/null
+++ b/tcl/target/cc26xx.cfg
@@ -0,0 +1,43 @@
+# Config for Texas Instruments low power SoC CC26xx family
+
+adapter_khz 100
+
+source [find target/icepick.cfg]
+source [find target/ti-cjtag.cfg]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME cc26xx
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4BA00477
+}
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+#
+# ICEpick-C (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x1B99A02F
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+# A start sequence is needed to change from cJTAG (Compact JTAG) to
+# 4-pin JTAG before talking via JTAG commands
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
+
+#
+# Cortex M3 target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg
new file mode 100755
index 000000000..7114b2adf
--- /dev/null
+++ b/tcl/target/ti-cjtag.cfg
@@ -0,0 +1,32 @@
+# A start sequence to change from cJTAG to 4-pin JTAG
+# This is needed for CC2538 and CC26xx to be able to communicate through JTAG
+# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information.
+proc ti_cjtag_to_4pin_jtag {jrc} {
+	# Bypass
+	irscan $jrc 0x3f -endstate RUN/IDLE
+	# Two zero bit scans and a one bit drshift
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+
+	# A two bit drhift and a 9 bit drshift
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+
+	# Bypass
+	irscan $jrc 0x3f -endstate RUN/IDLE
+
+	# Set ICEPick IDCODE in data register
+	irscan $jrc 0x04 -endstate RUN/IDLE
+}