- armv7m control register now set as dirty when switching context
- armv7m added core_mode to cortex_m3_debug_entry DEBUG msg - cortex_m3 changed WARNINGS to DEBUG msg in cortex_m3_resume git-svn-id: svn://svn.berlios.de/openocd/trunk@519 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak
parent
5a4525613d
commit
4622cb15a9
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@ -169,7 +169,7 @@ int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
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}
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/* Mark registers in new context as dirty to force reload when run */
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for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
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for (i = 0; i < armv7m->core_cache->num_regs; i++)
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{
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armv7m->core_cache->reg_list[i].dirty = 1;
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}
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@ -203,11 +203,11 @@ int armv7m_restore_context(target_t *target)
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return ERROR_OK;
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}
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/* Core state functions */
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char enamebuf[32];
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char *armv7m_exception_string(int number)
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{
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static char enamebuf[32];
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if ((number < 0) | (number > 511))
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return "Invalid exception";
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if (number < 16)
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@ -329,7 +329,6 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
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{
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if (i < ARMV7NUMCOREREGS)
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(*reg_list)[i] = &armv7m->process_context->reg_list[i];
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/* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
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else
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(*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
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}
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@ -344,15 +343,9 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
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enum armv7m_state core_state = armv7m->core_state;
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enum armv7m_mode core_mode = armv7m->core_mode;
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int retval = ERROR_OK;
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u32 pc;
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int exit_breakpoint_size = 0;
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int i;
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armv7m->core_state = core_state;
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armv7m->core_mode = core_mode;
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if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
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{
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@ -397,8 +390,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
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}
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/* ARMV7M always runs in Thumb state */
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exit_breakpoint_size = 2;
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if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
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if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
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{
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ERROR("can't add breakpoint to finish algorithm execution");
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return ERROR_TARGET_FAILURE;
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@ -188,13 +188,13 @@ int cortex_m3_endreset_event(target_t *target)
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target_write_u32(target, FP_CTRL, 3);
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/* Restore FPB registers */
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for ( i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
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for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
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{
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target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
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}
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/* Restore DWT registers */
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for ( i = 0; i < cortex_m3->dwt_num_comp; i++)
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for (i = 0; i < cortex_m3->dwt_num_comp; i++)
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{
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target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp);
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target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask);
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@ -311,16 +311,16 @@ int cortex_m3_debug_entry(target_t *target)
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return retval;
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/* Examine target state and mode */
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/* First load register acessible through core debug port*/
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/* First load register acessible through core debug port*/
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for (i = 0; i < ARMV7M_PRIMASK; i++)
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{
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if (!armv7m->core_cache->reg_list[i].valid)
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armv7m->read_core_reg(target, i);
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armv7m->read_core_reg(target, i);
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}
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xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
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/* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/
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/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
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if (xPSR & 0xf00)
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{
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armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
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@ -342,7 +342,8 @@ int cortex_m3_debug_entry(target_t *target)
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cortex_m3_examine_exception_reason(target);
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}
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DEBUG("entered debug state at PC 0x%x, target->state: %s ", *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
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DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \
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*(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
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if (armv7m->post_debug_entry)
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armv7m->post_debug_entry(target);
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@ -557,7 +558,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
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/* Check that we are using process_context, or change and print warning */
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if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
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{
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WARNING("Incorrect context in resume");
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DEBUG("Incorrect context in resume");
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armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
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}
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@ -565,7 +566,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
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cortex_m3_enable_breakpoints(target);
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cortex_m3_enable_watchpoints(target);
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/* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */
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/* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */
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}
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dcb_dhcsr = DBGKEY | C_DEBUGEN;
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@ -574,7 +575,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
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/* Check that we are using debug_context, or change and print warning */
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if (armv7m_get_context(target) != ARMV7M_DEBUG_CONTEXT)
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{
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WARNING("Incorrect context in debug_exec resume");
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DEBUG("Incorrect context in debug_exec resume");
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armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
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}
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/* Disable interrupts */
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@ -1450,7 +1451,6 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
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armv7m->arch_info = cortex_m3;
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armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
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armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
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/* armv7m->full_context = cortex_m3_full_context; */
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target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
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@ -1500,7 +1500,7 @@ int handle_poll_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
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if (argc == 0)
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{
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target->type->poll(target);
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target_arch_state(target);
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target_arch_state(target);
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}
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else
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{
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