From 4626af440122272a6c18ad293edc81d3051d83ec Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 18 Nov 2021 12:29:49 +0100 Subject: [PATCH] doc: fix typos in commands definition Change-Id: Ie07260f229c6bd227bae0bf3dd97d29bf84c72ec Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/6725 Tested-by: jenkins Reviewed-by: Tomas Vanek --- doc/openocd.texi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/doc/openocd.texi b/doc/openocd.texi index 9ff2e2e52..0ab4b36ac 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -2833,7 +2833,7 @@ Reset the current configuration. @deffn {Command} {jlink config write} Write the current configuration to the internal persistent storage. @end deffn -@deffn {Command} {jlink emucom write } +@deffn {Command} {jlink emucom write} Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal pairs. @@ -2843,7 +2843,7 @@ the EMUCOM channel 0x10: > jlink emucom write 0x10 aa0b23 @end example @end deffn -@deffn {Command} {jlink emucom read } +@deffn {Command} {jlink emucom read} Read data from an EMUCOM channel. The read data is encoded as hexadecimal pairs. @@ -7206,7 +7206,7 @@ as per the following example. flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME @end example -@deffn {Command} {stm32f2x otp } num (@option{enable}|@option{disable}|@option{show}) +@deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show}) Enables or disables OTP write commands for bank @var{num}. The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @@ -7643,7 +7643,7 @@ Some tms470-specific commands are defined: Saves programming keys in a register, to enable flash erase and write commands. @end deffn -@deffn {Command} {tms470 osc_mhz} clock_mhz +@deffn {Command} {tms470 osc_megahertz} clock_mhz Reports the clock speed, which is used to calculate timings. @end deffn @@ -8678,7 +8678,7 @@ If the control block location is not known, OpenOCD starts searching for it. Stop RTT. @end deffn -@deffn {Command} {rtt polling_interval [interval]} +@deffn {Command} {rtt polling_interval} [interval] Display the polling interval. If @var{interval} is provided, set the polling interval. The polling interval determines (in milliseconds) how often the up-channels are @@ -9026,7 +9026,7 @@ Enable (@option{on}) or disable (@option{off}) the CTI. Displays a register dump of the CTI. @end deffn -@deffn {Command} {$cti_name write } @var{reg_name} @var{value} +@deffn {Command} {$cti_name write} @var{reg_name} @var{value} Write @var{value} to the CTI register with the symbolic name @var{reg_name}. @end deffn @@ -9533,7 +9533,7 @@ cores @emph{except the ARM1176} use the same six bits. display information about target caches @end deffn -@deffn {Command} {cortex_a dacrfixup [@option{on}|@option{off}]} +@deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}] Work around issues with software breakpoints when the program text is mapped read-only by the operating system. This option sets the CP15 DACR to "all-manager" to bypass MMU permission checks on memory access. @@ -9571,12 +9571,12 @@ possible (4096) entries are printed. @subsection ARMv7-R specific commands @cindex Cortex-R -@deffn {Command} {cortex_r dbginit} +@deffn {Command} {cortex_r4 dbginit} Initialize core debug Enables debug by unlocking the Software Lock and clearing sticky powerdown indications @end deffn -@deffn {Command} {cortex_r maskisr} [@option{on}|@option{off}] +@deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}] Selects whether interrupts will be processed when single stepping @end deffn