esirisc: support eSi-RISC targets
eSi-RISC is a highly configurable microprocessor architecture for embedded systems provided by EnSilica. This patch adds support for 32-bit targets and also includes an internal flash driver and uC/OS-III RTOS support. This is a non-traditional target and required a number of additional changes to support non-linear register numbers and the 'p' packet in RTOS support for proper integration into EnSilica's GDB port. Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4660 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion
Matthias Welwarsky
parent
e72b2601e7
commit
4ab75a3634
15
README
15
README
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@ -117,17 +117,18 @@ Debug targets
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-------------
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ARM11, ARM7, ARM9, AVR32, Cortex-A, Cortex-R, Cortex-M, LS102x-SAP,
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Feroceon/Dragonite, DSP563xx, DSP5680xx, FA526, MIPS EJTAG, NDS32,
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XScale, Intel Quark.
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Feroceon/Dragonite, DSP563xx, DSP5680xx, EnSilica eSi-RISC, FA526, MIPS
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EJTAG, NDS32, XScale, Intel Quark.
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Flash drivers
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-------------
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ADUC702x, AT91SAM, ATH79, AVR, CFI, DSP5680xx, EFM32, EM357, FM3, FM4, Kinetis,
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LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPCSPIFI, Marvell QSPI,
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Milandr, NIIET, NuMicro, PIC32mx, PSoC4, PSoC5LP, SiM3x, Stellaris, STM32,
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STMSMI, STR7x, STR9x, nRF51; NAND controllers of AT91SAM9, LPC3180, LPC32xx,
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i.MX31, MXC, NUC910, Orion/Kirkwood, S3C24xx, S3C6400, XMC1xxx, XMC4xxx.
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ADUC702x, AT91SAM, ATH79, AVR, CFI, DSP5680xx, EFM32, EM357, eSi-TSMC,
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FM3, FM4, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPCSPIFI,
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Marvell QSPI, Milandr, NIIET, NuMicro, PIC32mx, PSoC4, PSoC5LP, SiM3x,
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Stellaris, STM32, STMSMI, STR7x, STR9x, nRF51; NAND controllers of
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AT91SAM9, LPC3180, LPC32xx, i.MX31, MXC, NUC910, Orion/Kirkwood,
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S3C24xx, S3C6400, XMC1xxx, XMC4xxx.
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==================
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@ -4275,6 +4275,8 @@ compact Thumb2 instruction set.
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@item @code{dragonite} -- resembles arm966e
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@item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
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(Support for this is still incomplete.)
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@item @code{esirisc} -- this is an EnSilica eSi-RISC core.
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The current implementation supports eSi-32xx cores.
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@item @code{fa526} -- resembles arm920 (w/o Thumb)
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@item @code{feroceon} -- resembles arm926
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@item @code{mips_m4k} -- a MIPS core
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@ -5647,6 +5649,27 @@ Note that in order for this command to take effect, the target needs to be reset
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supported.}
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@end deffn
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@deffn {Flash Driver} esirisc
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Members of the eSi-RISC family may optionally include internal flash programmed
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via the eSi-TSMC Flash interface. Additional parameters are required to
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configure the driver: @option{cfg_address} is the base address of the
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configuration register interface, @option{clock_hz} is the expected clock
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frequency, and @option{wait_states} is the number of configured read wait states.
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@example
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flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 $_TARGETNAME cfg_address clock_hz wait_states
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@end example
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@deffn Command {esirisc_flash mass_erase} (bank_id)
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Erases all pages in data memory for the bank identified by @option{bank_id}.
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@end deffn
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@deffn Command {esirisc_flash ref_erase} (bank_id)
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Erases the reference cell for the bank identified by @option{bank_id}. This is
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an uncommon operation.
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@end deffn
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@end deffn
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@deffn {Flash Driver} fm3
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All members of the FM3 microcontroller family from Fujitsu
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include internal flash and use ARM Cortex-M3 cores.
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@ -8933,6 +8956,29 @@ Selects whether interrupts will be processed when single stepping. The default c
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@option{on}.
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@end deffn
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@section EnSilica eSi-RISC Architecture
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eSi-RISC is a highly configurable microprocessor architecture for embedded systems
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provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
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@subsection esirisc specific commands
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@deffn Command {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
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Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
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option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
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@end deffn
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@deffn Command {esirisc flush_caches}
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Flush instruction and data caches. This command requires that the target is halted
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when the command is issued and configured with an instruction or data cache.
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@end deffn
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@deffn Command {esirisc hwdc} (@option{all}|@option{none}|mask ...)
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Configure hardware debug control. The HWDC register controls which exceptions return
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control back to the debugger. Possible masks are @option{all}, @option{none},
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@option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
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By default, @option{reset}, @option{error}, and @option{debug} are enabled.
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@end deffn
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@section Intel Architecture
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Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
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@ -25,6 +25,7 @@ NOR_DRIVERS = \
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%D%/dsp5680xx_flash.c \
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%D%/efm32.c \
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%D%/em357.c \
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%D%/esirisc_flash.c \
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%D%/faux.c \
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%D%/fm3.c \
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%D%/fm4.c \
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@ -38,6 +38,7 @@ extern struct flash_driver cfi_flash;
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extern struct flash_driver dsp5680xx_flash;
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extern struct flash_driver efm32_flash;
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extern struct flash_driver em357_flash;
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extern struct flash_driver esirisc_flash;
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extern struct flash_driver faux_flash;
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extern struct flash_driver fm3_flash;
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extern struct flash_driver fm4_flash;
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@ -103,6 +104,7 @@ static struct flash_driver *flash_drivers[] = {
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&dsp5680xx_flash,
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&efm32_flash,
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&em357_flash,
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&esirisc_flash,
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&faux_flash,
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&fm3_flash,
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&fm4_flash,
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@ -0,0 +1,621 @@
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/***************************************************************************
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* Copyright (C) 2018 by Square, Inc. *
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* Steven Stallion <stallion@squareup.com> *
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* James Zhao <hjz@squareup.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <flash/common.h>
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#include <flash/nor/imp.h>
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#include <helper/command.h>
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#include <helper/log.h>
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#include <helper/time_support.h>
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#include <helper/types.h>
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#include <target/esirisc.h>
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#include <target/target.h>
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/* eSi-TSMC Flash Registers */
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#define CONTROL 0x00 /* Control Register */
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#define TIMING0 0x04 /* Timing Register 0 */
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#define TIMING1 0x08 /* Timing Register 1 */
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#define TIMING2 0x0c /* Timing Register 2 */
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#define UNLOCK1 0x18 /* Unlock 1 */
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#define UNLOCK2 0x1c /* Unlock 2 */
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#define ADDRESS 0x20 /* Erase/Program Address */
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#define PB_DATA 0x24 /* Program Buffer Data */
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#define PB_INDEX 0x28 /* Program Buffer Index */
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#define STATUS 0x2c /* Status Register */
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#define REDUN_0 0x30 /* Redundant Address 0 */
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#define REDUN_1 0x34 /* Redundant Address 1 */
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/* Control Fields */
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#define CONTROL_SLM (1<<0) /* Sleep Mode */
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#define CONTROL_WP (1<<1) /* Register Write Protect */
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#define CONTROL_E (1<<3) /* Erase */
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#define CONTROL_EP (1<<4) /* Erase Page */
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#define CONTROL_P (1<<5) /* Program Flash */
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#define CONTROL_ERC (1<<6) /* Erase Reference Cell */
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#define CONTROL_R (1<<7) /* Recall Trim Code */
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#define CONTROL_AP (1<<8) /* Auto-Program */
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/* Timing Fields */
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#define TIMING0_R(x) (((x) << 0) & 0x3f) /* Read Wait States */
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#define TIMING0_F(x) (((x) << 16) & 0xffff0000) /* Tnvh Clock Cycles */
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#define TIMING1_E(x) (((x) << 0) & 0xffffff) /* Tme/Terase/Tre Clock Cycles */
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#define TIMING2_P(x) (((x) << 0) & 0xffff) /* Tprog Clock Cycles */
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#define TIMING2_H(x) (((x) << 16) & 0xff0000) /* Clock Cycles in 100ns */
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#define TIMING2_T(x) (((x) << 24) & 0xf000000) /* Clock Cycles in 10ns */
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/* Status Fields */
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#define STATUS_BUSY (1<<0) /* Busy (Erase/Program) */
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#define STATUS_WER (1<<1) /* Write Protect Error */
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#define STATUS_DR (1<<2) /* Disable Redundancy */
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#define STATUS_DIS (1<<3) /* Discharged */
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#define STATUS_BO (1<<4) /* Brown Out */
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/* Redundant Address Fields */
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#define REDUN_R (1<<0) /* Used */
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#define REDUN_P(x) (((x) << 12) & 0x7f000) /* Redundant Page Address */
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/*
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* The eSi-TSMC Flash manual provides two sets of timings based on the
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* underlying flash process. By default, 90nm is assumed.
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*/
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#if 0 /* 55nm */
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#define TNVH 5000 /* 5us */
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#define TME 80000000 /* 80ms */
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#define TERASE 160000000 /* 160ms */
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#define TRE 100000000 /* 100ms */
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#define TPROG 8000 /* 8us */
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#else /* 90nm */
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#define TNVH 5000 /* 5us */
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#define TME 20000000 /* 20ms */
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#define TERASE 40000000 /* 40ms */
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#define TRE 40000000 /* 40ms */
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#define TPROG 40000 /* 40us */
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#endif
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#define CONTROL_TIMEOUT 5000 /* 5s */
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#define PAGE_SIZE 4096
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#define PB_MAX 32
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#define NUM_NS_PER_S 1000000000ULL
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struct esirisc_flash_bank {
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bool probed;
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uint32_t cfg;
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uint32_t clock;
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uint32_t wait_states;
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};
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FLASH_BANK_COMMAND_HANDLER(esirisc_flash_bank_command)
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{
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struct esirisc_flash_bank *esirisc_info;
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if (CMD_ARGC < 9)
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return ERROR_COMMAND_SYNTAX_ERROR;
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esirisc_info = calloc(1, sizeof(struct esirisc_flash_bank));
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], esirisc_info->cfg);
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], esirisc_info->clock);
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], esirisc_info->wait_states);
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bank->driver_priv = esirisc_info;
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return ERROR_OK;
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}
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/*
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* Register writes are ignored if the control.WP flag is set; the
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* following sequence is required to modify this flag even when
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* protection is disabled.
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*/
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static int esirisc_flash_unlock(struct flash_bank *bank)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0x7123);
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target_write_u32(target, esirisc_info->cfg + UNLOCK2, 0x812a);
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target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0xbee1);
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return ERROR_OK;
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}
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static int esirisc_flash_disable_protect(struct flash_bank *bank)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t control;
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target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
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if (!(control & CONTROL_WP))
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return ERROR_OK;
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esirisc_flash_unlock(bank);
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control &= ~CONTROL_WP;
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target_write_u32(target, esirisc_info->cfg + CONTROL, control);
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return ERROR_OK;
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}
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static int esirisc_flash_enable_protect(struct flash_bank *bank)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t control;
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target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
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if (control & CONTROL_WP)
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return ERROR_OK;
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esirisc_flash_unlock(bank);
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control |= CONTROL_WP;
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target_write_u32(target, esirisc_info->cfg + CONTROL, control);
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return ERROR_OK;
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}
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static int esirisc_flash_check_status(struct flash_bank *bank)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t status;
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target_read_u32(target, esirisc_info->cfg + STATUS, &status);
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if (status & STATUS_WER) {
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LOG_ERROR("%s: bad status: 0x%" PRIx32, bank->name, status);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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return ERROR_OK;
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}
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static int esirisc_flash_clear_status(struct flash_bank *bank)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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target_write_u32(target, esirisc_info->cfg + STATUS, STATUS_WER);
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return ERROR_OK;
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}
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static int esirisc_flash_wait(struct flash_bank *bank, int ms)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t status;
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int64_t t;
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t = timeval_ms();
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for (;;) {
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target_read_u32(target, esirisc_info->cfg + STATUS, &status);
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if (!(status & STATUS_BUSY))
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return ERROR_OK;
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if ((timeval_ms() - t) > ms)
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return ERROR_TARGET_TIMEOUT;
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keep_alive();
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}
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}
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static int esirisc_flash_control(struct flash_bank *bank, uint32_t control)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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esirisc_flash_clear_status(bank);
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target_write_u32(target, esirisc_info->cfg + CONTROL, control);
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int retval = esirisc_flash_wait(bank, CONTROL_TIMEOUT);
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if (retval != ERROR_OK) {
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LOG_ERROR("%s: control timed out: 0x%" PRIx32, bank->name, control);
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return retval;
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}
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return esirisc_flash_check_status(bank);
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}
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static int esirisc_flash_recall(struct flash_bank *bank)
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{
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return esirisc_flash_control(bank, CONTROL_R);
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}
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static int esirisc_flash_erase(struct flash_bank *bank, int first, int last)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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int retval = ERROR_OK;
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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esirisc_flash_disable_protect(bank);
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for (int page = first; page < last; ++page) {
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uint32_t address = page * PAGE_SIZE;
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target_write_u32(target, esirisc_info->cfg + ADDRESS, address);
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retval = esirisc_flash_control(bank, CONTROL_EP);
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if (retval != ERROR_OK) {
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LOG_ERROR("%s: failed to erase address: 0x%" PRIx32, bank->name, address);
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break;
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}
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}
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esirisc_flash_enable_protect(bank);
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return retval;
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}
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static int esirisc_flash_mass_erase(struct flash_bank *bank)
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{
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struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
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struct target *target = bank->target;
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int retval;
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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esirisc_flash_disable_protect(bank);
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target_write_u32(target, esirisc_info->cfg + ADDRESS, 0);
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retval = esirisc_flash_control(bank, CONTROL_E);
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if (retval != ERROR_OK)
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LOG_ERROR("%s: failed to mass erase", bank->name);
|
||||
|
||||
esirisc_flash_enable_protect(bank);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* Per TSMC, the reference cell should be erased once per sample. This
|
||||
* is typically done during wafer sort, however we include support for
|
||||
* those that may need to calibrate flash at a later time.
|
||||
*/
|
||||
static int esirisc_flash_ref_erase(struct flash_bank *bank)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
int retval;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
|
||||
esirisc_flash_disable_protect(bank);
|
||||
|
||||
retval = esirisc_flash_control(bank, CONTROL_ERC);
|
||||
if (retval != ERROR_OK)
|
||||
LOG_ERROR("%s: failed to erase reference cell", bank->name);
|
||||
|
||||
esirisc_flash_enable_protect(bank);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int esirisc_flash_protect(struct flash_bank *bank, int set, int first, int last)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
|
||||
if (set)
|
||||
esirisc_flash_enable_protect(bank);
|
||||
else
|
||||
esirisc_flash_disable_protect(bank);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esirisc_flash_fill_pb(struct flash_bank *bank,
|
||||
const uint8_t *buffer, uint32_t count)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
struct target *target = bank->target;
|
||||
struct esirisc_common *esirisc = target_to_esirisc(target);
|
||||
|
||||
/*
|
||||
* The pb_index register is auto-incremented when pb_data is written
|
||||
* and should be cleared before each operation.
|
||||
*/
|
||||
target_write_u32(target, esirisc_info->cfg + PB_INDEX, 0);
|
||||
|
||||
/*
|
||||
* The width of the pb_data register depends on the underlying
|
||||
* target; writing one byte at a time incurs a significant
|
||||
* performance penalty and should be avoided.
|
||||
*/
|
||||
while (count > 0) {
|
||||
uint32_t max_bytes = DIV_ROUND_UP(esirisc->num_bits, 8);
|
||||
uint32_t num_bytes = MIN(count, max_bytes);
|
||||
|
||||
target_write_buffer(target, esirisc_info->cfg + PB_DATA, num_bytes, buffer);
|
||||
|
||||
buffer += num_bytes;
|
||||
count -= num_bytes;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esirisc_flash_write(struct flash_bank *bank,
|
||||
const uint8_t *buffer, uint32_t offset, uint32_t count)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
struct target *target = bank->target;
|
||||
int retval = ERROR_OK;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
|
||||
esirisc_flash_disable_protect(bank);
|
||||
|
||||
/*
|
||||
* The address register is auto-incremented based on the contents of
|
||||
* the pb_index register after each operation completes. It can be
|
||||
* set once provided pb_index is cleared before each operation.
|
||||
*/
|
||||
target_write_u32(target, esirisc_info->cfg + ADDRESS, offset);
|
||||
|
||||
/*
|
||||
* Care must be taken when filling the program buffer; a maximum of
|
||||
* 32 bytes may be written at a time and may not cross a 32-byte
|
||||
* boundary based on the current offset.
|
||||
*/
|
||||
while (count > 0) {
|
||||
uint32_t max_bytes = PB_MAX - (offset & 0x1f);
|
||||
uint32_t num_bytes = MIN(count, max_bytes);
|
||||
|
||||
esirisc_flash_fill_pb(bank, buffer, num_bytes);
|
||||
|
||||
retval = esirisc_flash_control(bank, CONTROL_P);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("%s: failed to program address: 0x%" PRIx32, bank->name, offset);
|
||||
break;
|
||||
}
|
||||
|
||||
buffer += num_bytes;
|
||||
offset += num_bytes;
|
||||
count -= num_bytes;
|
||||
}
|
||||
|
||||
esirisc_flash_enable_protect(bank);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static uint32_t esirisc_flash_num_cycles(struct flash_bank *bank, uint64_t ns)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
|
||||
/* apply scaling factor to avoid truncation */
|
||||
uint64_t hz = (uint64_t)esirisc_info->clock * 1000;
|
||||
uint64_t num_cycles = ((hz / NUM_NS_PER_S) * ns) / 1000;
|
||||
|
||||
if (hz % NUM_NS_PER_S > 0)
|
||||
num_cycles++;
|
||||
|
||||
return num_cycles;
|
||||
}
|
||||
|
||||
static int esirisc_flash_init(struct flash_bank *bank)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
struct target *target = bank->target;
|
||||
uint32_t value;
|
||||
int retval;
|
||||
|
||||
esirisc_flash_disable_protect(bank);
|
||||
|
||||
/* initialize timing registers */
|
||||
value = TIMING0_F(esirisc_flash_num_cycles(bank, TNVH)) |
|
||||
TIMING0_R(esirisc_info->wait_states);
|
||||
|
||||
LOG_DEBUG("TIMING0: 0x%" PRIx32, value);
|
||||
target_write_u32(target, esirisc_info->cfg + TIMING0, value);
|
||||
|
||||
value = TIMING1_E(esirisc_flash_num_cycles(bank, TERASE));
|
||||
|
||||
LOG_DEBUG("TIMING1: 0x%" PRIx32, value);
|
||||
target_write_u32(target, esirisc_info->cfg + TIMING1, value);
|
||||
|
||||
value = TIMING2_T(esirisc_flash_num_cycles(bank, 10)) |
|
||||
TIMING2_H(esirisc_flash_num_cycles(bank, 100)) |
|
||||
TIMING2_P(esirisc_flash_num_cycles(bank, TPROG));
|
||||
|
||||
LOG_DEBUG("TIMING2: 0x%" PRIx32, value);
|
||||
target_write_u32(target, esirisc_info->cfg + TIMING2, value);
|
||||
|
||||
/* recall trim code */
|
||||
retval = esirisc_flash_recall(bank);
|
||||
if (retval != ERROR_OK)
|
||||
LOG_ERROR("%s: failed to recall trim code", bank->name);
|
||||
|
||||
esirisc_flash_enable_protect(bank);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int esirisc_flash_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
struct target *target = bank->target;
|
||||
int retval;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
|
||||
bank->num_sectors = bank->size / PAGE_SIZE;
|
||||
bank->sectors = alloc_block_array(0, PAGE_SIZE, bank->num_sectors);
|
||||
|
||||
/*
|
||||
* Register write protection is enforced using a single protection
|
||||
* block for the entire bank. This is as good as it gets.
|
||||
*/
|
||||
bank->num_prot_blocks = 1;
|
||||
bank->prot_blocks = alloc_block_array(0, bank->size, bank->num_prot_blocks);
|
||||
|
||||
retval = esirisc_flash_init(bank);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("%s: failed to initialize bank", bank->name);
|
||||
return retval;
|
||||
}
|
||||
|
||||
esirisc_info->probed = true;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esirisc_flash_auto_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
|
||||
if (esirisc_info->probed)
|
||||
return ERROR_OK;
|
||||
|
||||
return esirisc_flash_probe(bank);
|
||||
}
|
||||
|
||||
static int esirisc_flash_protect_check(struct flash_bank *bank)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
struct target *target = bank->target;
|
||||
uint32_t control;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
|
||||
target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
|
||||
|
||||
/* single protection block (also see: esirisc_flash_probe()) */
|
||||
bank->prot_blocks[0].is_protected = !!(control & CONTROL_WP);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esirisc_flash_info(struct flash_bank *bank, char *buf, int buf_size)
|
||||
{
|
||||
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
|
||||
|
||||
snprintf(buf, buf_size,
|
||||
"%4s cfg at 0x%" PRIx32 ", clock %" PRId32 ", wait_states %" PRId32,
|
||||
"", /* align with first line */
|
||||
esirisc_info->cfg,
|
||||
esirisc_info->clock,
|
||||
esirisc_info->wait_states);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(handle_esirisc_flash_mass_erase_command)
|
||||
{
|
||||
struct flash_bank *bank;
|
||||
int retval;
|
||||
|
||||
if (CMD_ARGC < 1)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = esirisc_flash_mass_erase(bank);
|
||||
|
||||
command_print(CMD_CTX, "mass erase %s",
|
||||
(retval == ERROR_OK) ? "successful" : "failed");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(handle_esirisc_flash_ref_erase_command)
|
||||
{
|
||||
struct flash_bank *bank;
|
||||
int retval;
|
||||
|
||||
if (CMD_ARGC < 1)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = esirisc_flash_ref_erase(bank);
|
||||
|
||||
command_print(CMD_CTX, "erase reference cell %s",
|
||||
(retval == ERROR_OK) ? "successful" : "failed");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static const struct command_registration esirisc_flash_exec_command_handlers[] = {
|
||||
{
|
||||
.name = "mass_erase",
|
||||
.handler = handle_esirisc_flash_mass_erase_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.help = "erases all pages in data memory",
|
||||
.usage = "bank_id",
|
||||
},
|
||||
{
|
||||
.name = "ref_erase",
|
||||
.handler = handle_esirisc_flash_ref_erase_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.help = "erases reference cell (uncommon)",
|
||||
.usage = "bank_id",
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
static const struct command_registration esirisc_flash_command_handlers[] = {
|
||||
{
|
||||
.name = "esirisc_flash",
|
||||
.mode = COMMAND_ANY,
|
||||
.help = "eSi-RISC flash command group",
|
||||
.usage = "",
|
||||
.chain = esirisc_flash_exec_command_handlers,
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
struct flash_driver esirisc_flash = {
|
||||
.name = "esirisc",
|
||||
.commands = esirisc_flash_command_handlers,
|
||||
.usage = "flash bank bank_id 'esirisc' base_address size_bytes 0 0 target "
|
||||
"cfg_address clock_hz wait_states",
|
||||
.flash_bank_command = esirisc_flash_bank_command,
|
||||
.erase = esirisc_flash_erase,
|
||||
.protect = esirisc_flash_protect,
|
||||
.write = esirisc_flash_write,
|
||||
.read = default_flash_read,
|
||||
.probe = esirisc_flash_probe,
|
||||
.auto_probe = esirisc_flash_auto_probe,
|
||||
.erase_check = default_flash_blank_check,
|
||||
.protect_check = esirisc_flash_protect_check,
|
||||
.info = esirisc_flash_info,
|
||||
};
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
#include <rtos/rtos.h>
|
||||
#include <rtos/rtos_standard_stackings.h>
|
||||
#include <target/armv7m.h>
|
||||
#include <target/esirisc.h>
|
||||
|
||||
static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[] = {
|
||||
{ ARMV7M_R0, 0x20, 32 }, /* r0 */
|
||||
|
|
@ -45,6 +46,27 @@ static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[]
|
|||
{ ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */
|
||||
};
|
||||
|
||||
static const struct stack_register_offset rtos_uCOS_III_eSi_RISC_stack_offsets[] = {
|
||||
{ ESIRISC_SP, -2, 32 }, /* sp */
|
||||
{ ESIRISC_RA, 0x48, 32 }, /* ra */
|
||||
{ ESIRISC_R2, 0x44, 32 }, /* r2 */
|
||||
{ ESIRISC_R3, 0x40, 32 }, /* r3 */
|
||||
{ ESIRISC_R4, 0x3c, 32 }, /* r4 */
|
||||
{ ESIRISC_R5, 0x38, 32 }, /* r5 */
|
||||
{ ESIRISC_R6, 0x34, 32 }, /* r6 */
|
||||
{ ESIRISC_R7, 0x30, 32 }, /* r7 */
|
||||
{ ESIRISC_R8, 0x2c, 32 }, /* r8 */
|
||||
{ ESIRISC_R9, 0x28, 32 }, /* r9 */
|
||||
{ ESIRISC_R10, 0x24, 32 }, /* r10 */
|
||||
{ ESIRISC_R11, 0x20, 32 }, /* r11 */
|
||||
{ ESIRISC_R12, 0x1c, 32 }, /* r12 */
|
||||
{ ESIRISC_R13, 0x18, 32 }, /* r13 */
|
||||
{ ESIRISC_R14, 0x14, 32 }, /* r14 */
|
||||
{ ESIRISC_R15, 0x10, 32 }, /* r15 */
|
||||
{ ESIRISC_PC, 0x04, 32 }, /* PC */
|
||||
{ ESIRISC_CAS, 0x08, 32 }, /* CAS */
|
||||
};
|
||||
|
||||
const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking = {
|
||||
0x40, /* stack_registers_size */
|
||||
-1, /* stack_growth_direction */
|
||||
|
|
@ -52,3 +74,11 @@ const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking = {
|
|||
rtos_generic_stack_align8, /* stack_alignment */
|
||||
rtos_uCOS_III_Cortex_M_stack_offsets /* register_offsets */
|
||||
};
|
||||
|
||||
const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking = {
|
||||
0x4c, /* stack_registers_size */
|
||||
-1, /* stack_growth_direction */
|
||||
ARRAY_SIZE(rtos_uCOS_III_eSi_RISC_stack_offsets), /* num_output_registers */
|
||||
NULL, /* stack_alignment */
|
||||
rtos_uCOS_III_eSi_RISC_stack_offsets /* register_offsets */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,5 +26,6 @@
|
|||
#include <rtos/rtos.h>
|
||||
|
||||
extern const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking;
|
||||
extern const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking;
|
||||
|
||||
#endif /* OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H */
|
||||
|
|
|
|||
|
|
@ -68,6 +68,20 @@ static const struct uCOS_III_params uCOS_III_params_list[] = {
|
|||
&rtos_uCOS_III_Cortex_M_stacking, /* stacking_info */
|
||||
0, /* num_threads */
|
||||
},
|
||||
{
|
||||
"esirisc", /* target_name */
|
||||
sizeof(uint32_t), /* pointer_width */
|
||||
0, /* thread_stack_offset */
|
||||
0, /* thread_name_offset */
|
||||
0, /* thread_state_offset */
|
||||
0, /* thread_priority_offset */
|
||||
0, /* thread_prev_offset */
|
||||
0, /* thread_next_offset */
|
||||
false, /* thread_offsets_updated */
|
||||
1, /* threadid_start */
|
||||
&rtos_uCOS_III_eSi_RISC_stacking, /* stacking_info */
|
||||
0, /* num_threads */
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const uCOS_III_symbol_list[] = {
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
|
|||
$(NDS32_SRC) \
|
||||
$(STM8_SRC) \
|
||||
$(INTEL_IA32_SRC) \
|
||||
$(ESIRISC_SRC) \
|
||||
%D%/avrt.c \
|
||||
%D%/dsp563xx.c \
|
||||
%D%/dsp563xx_once.c \
|
||||
|
|
@ -139,6 +140,10 @@ INTEL_IA32_SRC = \
|
|||
%D%/lakemont.c \
|
||||
%D%/x86_32_common.c
|
||||
|
||||
ESIRISC_SRC = \
|
||||
%D%/esirisc.c \
|
||||
%D%/esirisc_jtag.c
|
||||
|
||||
%C%_libtarget_la_SOURCES += \
|
||||
%D%/algorithm.h \
|
||||
%D%/arm.h \
|
||||
|
|
@ -218,7 +223,10 @@ INTEL_IA32_SRC = \
|
|||
%D%/stm8.h \
|
||||
%D%/lakemont.h \
|
||||
%D%/x86_32_common.h \
|
||||
%D%/arm_cti.h
|
||||
%D%/arm_cti.h \
|
||||
%D%/esirisc.h \
|
||||
%D%/esirisc_jtag.h \
|
||||
%D%/esirisc_regs.h
|
||||
|
||||
include %D%/openrisc/Makefile.am
|
||||
include %D%/riscv/Makefile.am
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,129 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2018 by Square, Inc. *
|
||||
* Steven Stallion <stallion@squareup.com> *
|
||||
* James Zhao <hjz@squareup.com> *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef OPENOCD_TARGET_ESIRISC_H
|
||||
#define OPENOCD_TARGET_ESIRISC_H
|
||||
|
||||
#include <target/breakpoints.h>
|
||||
#include <target/register.h>
|
||||
#include <target/target.h>
|
||||
|
||||
#include "esirisc_jtag.h"
|
||||
#include "esirisc_regs.h"
|
||||
|
||||
#define MAX_BREAKPOINTS 8
|
||||
#define MAX_WATCHPOINTS 8
|
||||
|
||||
/* Exception IDs */
|
||||
#define EID_RESET 0x00
|
||||
#define EID_HARDWARE_FAILURE 0x01
|
||||
#define EID_NMI 0x02
|
||||
#define EID_INST_BREAKPOINT 0x03
|
||||
#define EID_DATA_BREAKPOINT 0x04
|
||||
#define EID_UNSUPPORTED 0x05
|
||||
#define EID_PRIVILEGE_VIOLATION 0x06
|
||||
#define EID_INST_BUS_ERROR 0x07
|
||||
#define EID_DATA_BUS_ERROR 0x08
|
||||
#define EID_ALIGNMENT_ERROR 0x09
|
||||
#define EID_ARITHMETIC_ERROR 0x0a
|
||||
#define EID_SYSTEM_CALL 0x0b
|
||||
#define EID_MEMORY_MANAGEMENT 0x0c
|
||||
#define EID_UNRECOVERABLE 0x0d
|
||||
#define EID_INTERRUPTn 0x20
|
||||
|
||||
/* Exception Entry Points */
|
||||
#define ENTRY_RESET 0x00
|
||||
#define ENTRY_UNRECOVERABLE 0x01
|
||||
#define ENTRY_HARDWARE_FAILURE 0x02
|
||||
#define ENTRY_RUNTIME 0x03
|
||||
#define ENTRY_MEMORY 0x04
|
||||
#define ENTRY_SYSCALL 0x05
|
||||
#define ENTRY_DEBUG 0x06
|
||||
#define ENTRY_NMI 0x07
|
||||
#define ENTRY_INTERRUPTn 0x08
|
||||
|
||||
/* Hardware Debug Control */
|
||||
#define HWDC_R (1<<4) /* Reset & Hardware Failure */
|
||||
#define HWDC_I (1<<3) /* Interrupts */
|
||||
#define HWDC_S (1<<2) /* System Calls */
|
||||
#define HWDC_E (1<<1) /* Program Errors */
|
||||
#define HWDC_D (1<<0) /* Debug Exceptions */
|
||||
|
||||
enum esirisc_cache {
|
||||
ESIRISC_CACHE_VON_NEUMANN,
|
||||
ESIRISC_CACHE_HARVARD,
|
||||
};
|
||||
|
||||
struct esirisc_common {
|
||||
struct target *target;
|
||||
struct esirisc_jtag jtag_info;
|
||||
enum esirisc_cache cache_arch;
|
||||
char *gdb_arch;
|
||||
|
||||
struct reg_cache *reg_cache;
|
||||
struct reg *epc;
|
||||
struct reg *ecas;
|
||||
struct reg *eid;
|
||||
struct reg *ed;
|
||||
uint32_t etc_save;
|
||||
uint32_t hwdc_save;
|
||||
|
||||
int num_bits;
|
||||
int num_regs;
|
||||
bool has_icache;
|
||||
bool has_dcache;
|
||||
int num_breakpoints;
|
||||
int num_watchpoints;
|
||||
|
||||
struct breakpoint *breakpoints_p[MAX_BREAKPOINTS];
|
||||
struct watchpoint *watchpoints_p[MAX_WATCHPOINTS];
|
||||
};
|
||||
|
||||
union esirisc_memory {
|
||||
uint32_t word;
|
||||
uint16_t hword;
|
||||
uint8_t byte;
|
||||
};
|
||||
|
||||
struct esirisc_reg {
|
||||
struct esirisc_common *esirisc;
|
||||
|
||||
uint8_t bank;
|
||||
uint8_t csr;
|
||||
|
||||
int (*read)(struct reg *reg);
|
||||
int (*write)(struct reg *reg);
|
||||
};
|
||||
|
||||
static inline struct esirisc_common *target_to_esirisc(struct target *target)
|
||||
{
|
||||
return (struct esirisc_common *)target->arch_info;
|
||||
}
|
||||
|
||||
static inline char *esirisc_cache_arch(struct esirisc_common *esirisc)
|
||||
{
|
||||
return esirisc->cache_arch == ESIRISC_CACHE_HARVARD ? "harvard" : "von_neumann";
|
||||
}
|
||||
|
||||
static inline bool esirisc_has_cache(struct esirisc_common *esirisc)
|
||||
{
|
||||
return esirisc->has_icache || esirisc->has_dcache;
|
||||
}
|
||||
|
||||
#endif /* OPENOCD_TARGET_ESIRISC_H */
|
||||
|
|
@ -0,0 +1,514 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2018 by Square, Inc. *
|
||||
* Steven Stallion <stallion@squareup.com> *
|
||||
* James Zhao <hjz@squareup.com> *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <helper/binarybuffer.h>
|
||||
#include <helper/log.h>
|
||||
#include <helper/types.h>
|
||||
#include <jtag/jtag.h>
|
||||
#include <jtag/commands.h>
|
||||
#include <jtag/interface.h>
|
||||
|
||||
#include "esirisc_jtag.h"
|
||||
|
||||
static void esirisc_jtag_set_instr(struct esirisc_jtag *jtag_info, uint32_t new_instr)
|
||||
{
|
||||
struct jtag_tap *tap = jtag_info->tap;
|
||||
|
||||
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
|
||||
struct scan_field field;
|
||||
uint8_t t[4];
|
||||
|
||||
field.num_bits = tap->ir_length;
|
||||
field.out_value = t;
|
||||
buf_set_u32(t, 0, field.num_bits, new_instr);
|
||||
field.in_value = NULL;
|
||||
|
||||
jtag_add_ir_scan(tap, &field, TAP_IDLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The data register is latched every 8 bits while in the Shift-DR state
|
||||
* (Update-DR is not supported). This necessitates prepending padding
|
||||
* bits to ensure data is aligned when multiple TAPs are present.
|
||||
*/
|
||||
static int esirisc_jtag_get_padding(void)
|
||||
{
|
||||
int padding = 0;
|
||||
int bypass_devices = 0;
|
||||
|
||||
for (struct jtag_tap *tap = jtag_tap_next_enabled(NULL); tap != NULL;
|
||||
tap = jtag_tap_next_enabled(tap))
|
||||
if (tap->bypass)
|
||||
bypass_devices++;
|
||||
|
||||
int num_bits = bypass_devices % 8;
|
||||
if (num_bits > 0)
|
||||
padding = 8 - num_bits;
|
||||
|
||||
return padding;
|
||||
}
|
||||
|
||||
static int esirisc_jtag_count_bits(int num_fields, struct scan_field *fields)
|
||||
{
|
||||
int bit_count = 0;
|
||||
|
||||
for (int i = 0; i < num_fields; ++i)
|
||||
bit_count += fields[i].num_bits;
|
||||
|
||||
return bit_count;
|
||||
}
|
||||
|
||||
/*
|
||||
* Data received from the target will be byte-stuffed if it contains
|
||||
* either the pad byte (0xAA) or stuffing marker (0x55). Buffers should
|
||||
* be sized twice the expected length to account for stuffing overhead.
|
||||
*/
|
||||
static void esirisc_jtag_unstuff(uint8_t *data, size_t len)
|
||||
{
|
||||
uint8_t *r, *w;
|
||||
uint8_t *end;
|
||||
|
||||
r = w = data;
|
||||
end = data + len;
|
||||
while (r < end) {
|
||||
if (*r == STUFF_MARKER) {
|
||||
r++; /* skip stuffing marker */
|
||||
assert(r < end);
|
||||
*w++ = *r++ ^ STUFF_MARKER;
|
||||
} else
|
||||
*w++ = *r++;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The eSi-Debug protocol defines a byte-oriented command/response
|
||||
* channel that operates over serial or JTAG. While not strictly
|
||||
* required, separate DR scans are used for sending and receiving data.
|
||||
* This allows the TAP to recover gracefully if the byte stream is
|
||||
* corrupted at the expense of sending additional padding bits.
|
||||
*/
|
||||
|
||||
static int esirisc_jtag_send(struct esirisc_jtag *jtag_info, uint8_t command,
|
||||
int num_out_fields, struct scan_field *out_fields)
|
||||
{
|
||||
int num_fields = 2 + num_out_fields;
|
||||
struct scan_field *fields = cmd_queue_alloc(num_fields * sizeof(struct scan_field));
|
||||
|
||||
esirisc_jtag_set_instr(jtag_info, INSTR_DEBUG);
|
||||
|
||||
fields[0].num_bits = esirisc_jtag_get_padding();
|
||||
fields[0].out_value = NULL;
|
||||
fields[0].in_value = NULL;
|
||||
|
||||
fields[1].num_bits = 8;
|
||||
fields[1].out_value = &command;
|
||||
fields[1].in_value = NULL;
|
||||
|
||||
/* append command data */
|
||||
for (int i = 0; i < num_out_fields; ++i)
|
||||
jtag_scan_field_clone(&fields[2+i], &out_fields[i]);
|
||||
|
||||
jtag_add_dr_scan(jtag_info->tap, num_fields, fields, TAP_IDLE);
|
||||
|
||||
return jtag_execute_queue();
|
||||
}
|
||||
|
||||
static int esirisc_jtag_recv(struct esirisc_jtag *jtag_info,
|
||||
int num_in_fields, struct scan_field *in_fields)
|
||||
{
|
||||
int num_in_bits = esirisc_jtag_count_bits(num_in_fields, in_fields);
|
||||
int num_in_bytes = DIV_ROUND_UP(num_in_bits, 8);
|
||||
|
||||
struct scan_field fields[3];
|
||||
uint8_t r[num_in_bytes * 2];
|
||||
|
||||
esirisc_jtag_set_instr(jtag_info, INSTR_DEBUG);
|
||||
|
||||
fields[0].num_bits = esirisc_jtag_get_padding() + 1;
|
||||
fields[0].out_value = NULL;
|
||||
fields[0].in_value = NULL;
|
||||
|
||||
fields[1].num_bits = 8;
|
||||
fields[1].out_value = NULL;
|
||||
fields[1].in_value = &jtag_info->status;
|
||||
|
||||
fields[2].num_bits = num_in_bits * 2;
|
||||
fields[2].out_value = NULL;
|
||||
fields[2].in_value = r;
|
||||
|
||||
jtag_add_dr_scan(jtag_info->tap, ARRAY_SIZE(fields), fields, TAP_IDLE);
|
||||
|
||||
int retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* unstuff response data and write back to caller */
|
||||
if (num_in_fields > 0) {
|
||||
esirisc_jtag_unstuff(r, ARRAY_SIZE(r));
|
||||
|
||||
int bit_count = 0;
|
||||
for (int i = 0; i < num_in_fields; ++i) {
|
||||
buf_set_buf(r, bit_count, in_fields[i].in_value, 0, in_fields[i].num_bits);
|
||||
bit_count += in_fields[i].num_bits;
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esirisc_jtag_check_status(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
uint8_t eid = esirisc_jtag_get_eid(jtag_info);
|
||||
if (eid != EID_NONE) {
|
||||
LOG_ERROR("esirisc_jtag: bad status: 0x%02" PRIx32 " (DA: %" PRId32 ", "
|
||||
"S: %" PRId32 ", EID: 0x%02" PRIx32 ")",
|
||||
jtag_info->status, esirisc_jtag_is_debug_active(jtag_info),
|
||||
esirisc_jtag_is_stopped(jtag_info), eid);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esirisc_jtag_send_and_recv(struct esirisc_jtag *jtag_info, uint8_t command,
|
||||
int num_out_fields, struct scan_field *out_fields,
|
||||
int num_in_fields, struct scan_field *in_fields)
|
||||
{
|
||||
int retval;
|
||||
|
||||
jtag_info->status = 0; /* clear status */
|
||||
|
||||
retval = esirisc_jtag_send(jtag_info, command, num_out_fields, out_fields);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("esirisc_jtag: send failed (command: 0x%02" PRIx32 ")", command);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
retval = esirisc_jtag_recv(jtag_info, num_in_fields, in_fields);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("esirisc_jtag: recv failed (command: 0x%02" PRIx32 ")", command);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
return esirisc_jtag_check_status(jtag_info);
|
||||
}
|
||||
|
||||
/*
|
||||
* Status is automatically updated after each command completes;
|
||||
* these functions make each field available to the caller.
|
||||
*/
|
||||
|
||||
bool esirisc_jtag_is_debug_active(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return !!(jtag_info->status & 1<<7); /* DA */
|
||||
}
|
||||
|
||||
bool esirisc_jtag_is_stopped(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return !!(jtag_info->status & 1<<6); /* S */
|
||||
}
|
||||
|
||||
uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return jtag_info->status & 0x3f; /* EID */
|
||||
}
|
||||
|
||||
/*
|
||||
* Most commands manipulate target data (eg. memory and registers); each
|
||||
* command returns a status byte that indicates success. Commands must
|
||||
* transmit multibyte values in big-endian order, however response
|
||||
* values are in little-endian order. Target endianness does not have an
|
||||
* effect on this ordering.
|
||||
*/
|
||||
|
||||
int esirisc_jtag_read_byte(struct esirisc_jtag *jtag_info, uint32_t address, uint8_t *data)
|
||||
{
|
||||
struct scan_field out_fields[1];
|
||||
uint8_t a[4];
|
||||
|
||||
out_fields[0].num_bits = 32;
|
||||
out_fields[0].out_value = a;
|
||||
h_u32_to_be(a, address);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
struct scan_field in_fields[1];
|
||||
uint8_t d[1];
|
||||
|
||||
in_fields[0].num_bits = 8;
|
||||
in_fields[0].out_value = NULL;
|
||||
in_fields[0].in_value = d;
|
||||
|
||||
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_BYTE,
|
||||
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
*data = *d;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esirisc_jtag_read_hword(struct esirisc_jtag *jtag_info, uint32_t address, uint16_t *data)
|
||||
{
|
||||
struct scan_field out_fields[1];
|
||||
uint8_t a[4];
|
||||
|
||||
out_fields[0].num_bits = 32;
|
||||
out_fields[0].out_value = a;
|
||||
h_u32_to_be(a, address);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
struct scan_field in_fields[1];
|
||||
uint8_t d[2];
|
||||
|
||||
in_fields[0].num_bits = 16;
|
||||
in_fields[0].out_value = NULL;
|
||||
in_fields[0].in_value = d;
|
||||
|
||||
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_HWORD,
|
||||
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
*data = le_to_h_u16(d);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esirisc_jtag_read_word(struct esirisc_jtag *jtag_info, uint32_t address, uint32_t *data)
|
||||
{
|
||||
struct scan_field out_fields[1];
|
||||
uint8_t a[4];
|
||||
|
||||
out_fields[0].num_bits = 32;
|
||||
out_fields[0].out_value = a;
|
||||
h_u32_to_be(a, address);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
struct scan_field in_fields[1];
|
||||
uint8_t d[4];
|
||||
|
||||
in_fields[0].num_bits = 32;
|
||||
in_fields[0].out_value = NULL;
|
||||
in_fields[0].in_value = d;
|
||||
|
||||
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_WORD,
|
||||
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
*data = le_to_h_u32(d);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esirisc_jtag_write_byte(struct esirisc_jtag *jtag_info, uint32_t address, uint8_t data)
|
||||
{
|
||||
struct scan_field out_fields[2];
|
||||
uint8_t a[4];
|
||||
|
||||
out_fields[0].num_bits = 32;
|
||||
out_fields[0].out_value = a;
|
||||
h_u32_to_be(a, address);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
out_fields[1].num_bits = 8;
|
||||
out_fields[1].out_value = &data;
|
||||
out_fields[1].in_value = NULL;
|
||||
|
||||
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_BYTE,
|
||||
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
|
||||
}
|
||||
|
||||
int esirisc_jtag_write_hword(struct esirisc_jtag *jtag_info, uint32_t address, uint16_t data)
|
||||
{
|
||||
struct scan_field out_fields[2];
|
||||
uint8_t a[4], d[2];
|
||||
|
||||
out_fields[0].num_bits = 32;
|
||||
out_fields[0].out_value = a;
|
||||
h_u32_to_be(a, address);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
out_fields[1].num_bits = 16;
|
||||
out_fields[1].out_value = d;
|
||||
h_u16_to_be(d, data);
|
||||
out_fields[1].in_value = NULL;
|
||||
|
||||
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_HWORD,
|
||||
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
|
||||
}
|
||||
|
||||
int esirisc_jtag_write_word(struct esirisc_jtag *jtag_info, uint32_t address, uint32_t data)
|
||||
{
|
||||
struct scan_field out_fields[2];
|
||||
uint8_t a[4], d[4];
|
||||
|
||||
out_fields[0].num_bits = 32;
|
||||
out_fields[0].out_value = a;
|
||||
h_u32_to_be(a, address);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
out_fields[1].num_bits = 32;
|
||||
out_fields[1].out_value = d;
|
||||
h_u32_to_be(d, data);
|
||||
out_fields[1].in_value = NULL;
|
||||
|
||||
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_WORD,
|
||||
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
|
||||
}
|
||||
|
||||
int esirisc_jtag_read_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t *data)
|
||||
{
|
||||
struct scan_field out_fields[1];
|
||||
|
||||
out_fields[0].num_bits = 8;
|
||||
out_fields[0].out_value = ®
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
struct scan_field in_fields[1];
|
||||
uint8_t d[4];
|
||||
|
||||
in_fields[0].num_bits = 32;
|
||||
in_fields[0].out_value = NULL;
|
||||
in_fields[0].in_value = d;
|
||||
|
||||
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_REG,
|
||||
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
*data = le_to_h_u32(d);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esirisc_jtag_write_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t data)
|
||||
{
|
||||
struct scan_field out_fields[2];
|
||||
uint8_t d[4];
|
||||
|
||||
out_fields[0].num_bits = 8;
|
||||
out_fields[0].out_value = ®
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
out_fields[1].num_bits = 32;
|
||||
out_fields[1].out_value = d;
|
||||
h_u32_to_be(d, data);
|
||||
out_fields[1].in_value = NULL;
|
||||
|
||||
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_REG,
|
||||
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
|
||||
}
|
||||
|
||||
int esirisc_jtag_read_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t csr, uint32_t *data)
|
||||
{
|
||||
struct scan_field out_fields[1];
|
||||
uint8_t c[2];
|
||||
|
||||
out_fields[0].num_bits = 16;
|
||||
out_fields[0].out_value = c;
|
||||
h_u16_to_be(c, (csr << 5) | bank);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
struct scan_field in_fields[1];
|
||||
uint8_t d[4];
|
||||
|
||||
in_fields[0].num_bits = 32;
|
||||
in_fields[0].out_value = NULL;
|
||||
in_fields[0].in_value = d;
|
||||
|
||||
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_CSR,
|
||||
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
*data = le_to_h_u32(d);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t csr, uint32_t data)
|
||||
{
|
||||
struct scan_field out_fields[2];
|
||||
uint8_t c[2], d[4];
|
||||
|
||||
out_fields[0].num_bits = 16;
|
||||
out_fields[0].out_value = c;
|
||||
h_u16_to_be(c, (csr << 5) | bank);
|
||||
out_fields[0].in_value = NULL;
|
||||
|
||||
out_fields[1].num_bits = 32;
|
||||
out_fields[1].out_value = d;
|
||||
h_u32_to_be(d, data);
|
||||
out_fields[1].in_value = NULL;
|
||||
|
||||
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_CSR,
|
||||
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* Control commands affect CPU operation; these commands send no data
|
||||
* and return a status byte.
|
||||
*/
|
||||
|
||||
static inline int esirisc_jtag_send_ctrl(struct esirisc_jtag *jtag_info, uint8_t command)
|
||||
{
|
||||
return esirisc_jtag_send_and_recv(jtag_info, command, 0, NULL, 0, NULL);
|
||||
}
|
||||
|
||||
int esirisc_jtag_enable_debug(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_ENABLE_DEBUG);
|
||||
}
|
||||
|
||||
int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_DISABLE_DEBUG);
|
||||
}
|
||||
|
||||
int esirisc_jtag_assert_reset(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_ASSERT_RESET);
|
||||
}
|
||||
|
||||
int esirisc_jtag_deassert_reset(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_DEASSERT_RESET);
|
||||
}
|
||||
|
||||
int esirisc_jtag_break(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_BREAK);
|
||||
}
|
||||
|
||||
int esirisc_jtag_continue(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_CONTINUE);
|
||||
}
|
||||
|
||||
int esirisc_jtag_flush_caches(struct esirisc_jtag *jtag_info)
|
||||
{
|
||||
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_FLUSH_CACHES);
|
||||
}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2018 by Square, Inc. *
|
||||
* Steven Stallion <stallion@squareup.com> *
|
||||
* James Zhao <hjz@squareup.com> *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef OPENOCD_TARGET_ESIRISC_JTAG_H
|
||||
#define OPENOCD_TARGET_ESIRISC_JTAG_H
|
||||
|
||||
#include <jtag/jtag.h>
|
||||
|
||||
/* TAP Instructions */
|
||||
#define INSTR_IDCODE 0x8
|
||||
#define INSTR_DEBUG 0x9
|
||||
#define INSTR_BYPASS 0xf
|
||||
#define INSTR_LENGTH 4
|
||||
|
||||
/* eSi-Debug Commands */
|
||||
#define DEBUG_NOP 0x00
|
||||
#define DEBUG_READ_BYTE 0x10
|
||||
#define DEBUG_READ_HWORD 0x20
|
||||
#define DEBUG_READ_WORD 0x30
|
||||
#define DEBUG_WRITE_BYTE 0x60
|
||||
#define DEBUG_WRITE_HWORD 0x70
|
||||
#define DEBUG_WRITE_WORD 0x80
|
||||
#define DEBUG_READ_REG 0xb0
|
||||
#define DEBUG_WRITE_REG 0xc0
|
||||
#define DEBUG_READ_CSR 0xd0
|
||||
#define DEBUG_WRITE_CSR 0xe0
|
||||
#define DEBUG_ENABLE_DEBUG 0xf0
|
||||
#define DEBUG_DISABLE_DEBUG 0xf2
|
||||
#define DEBUG_ASSERT_RESET 0xf4
|
||||
#define DEBUG_DEASSERT_RESET 0xf6
|
||||
#define DEBUG_BREAK 0xf8
|
||||
#define DEBUG_CONTINUE 0xfa
|
||||
#define DEBUG_FLUSH_CACHES 0xfc
|
||||
|
||||
/* Exception IDs */
|
||||
#define EID_OVERFLOW 0x3d
|
||||
#define EID_CANT_DEBUG 0x3e
|
||||
#define EID_NONE 0x3f
|
||||
|
||||
/* Byte Stuffing */
|
||||
#define STUFF_MARKER 0x55
|
||||
#define PAD_BYTE 0xaa
|
||||
|
||||
struct esirisc_jtag {
|
||||
struct jtag_tap *tap;
|
||||
uint8_t status;
|
||||
};
|
||||
|
||||
bool esirisc_jtag_is_debug_active(struct esirisc_jtag *jtag_info);
|
||||
bool esirisc_jtag_is_stopped(struct esirisc_jtag *jtag_info);
|
||||
uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info);
|
||||
|
||||
int esirisc_jtag_read_byte(struct esirisc_jtag *jtag_info,
|
||||
uint32_t address, uint8_t *data);
|
||||
int esirisc_jtag_read_hword(struct esirisc_jtag *jtag_info,
|
||||
uint32_t address, uint16_t *data);
|
||||
int esirisc_jtag_read_word(struct esirisc_jtag *jtag_info,
|
||||
uint32_t address, uint32_t *data);
|
||||
|
||||
int esirisc_jtag_write_byte(struct esirisc_jtag *jtag_info,
|
||||
uint32_t address, uint8_t data);
|
||||
int esirisc_jtag_write_hword(struct esirisc_jtag *jtag_info,
|
||||
uint32_t address, uint16_t data);
|
||||
int esirisc_jtag_write_word(struct esirisc_jtag *jtag_info,
|
||||
uint32_t address, uint32_t data);
|
||||
|
||||
int esirisc_jtag_read_reg(struct esirisc_jtag *jtag_info,
|
||||
uint8_t reg, uint32_t *data);
|
||||
int esirisc_jtag_write_reg(struct esirisc_jtag *jtag_info,
|
||||
uint8_t reg, uint32_t data);
|
||||
|
||||
int esirisc_jtag_read_csr(struct esirisc_jtag *jtag_info,
|
||||
uint8_t bank, uint8_t csr, uint32_t *data);
|
||||
int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info,
|
||||
uint8_t bank, uint8_t csr, uint32_t data);
|
||||
|
||||
int esirisc_jtag_enable_debug(struct esirisc_jtag *jtag_info);
|
||||
int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info);
|
||||
|
||||
int esirisc_jtag_assert_reset(struct esirisc_jtag *jtag_info);
|
||||
int esirisc_jtag_deassert_reset(struct esirisc_jtag *jtag_info);
|
||||
|
||||
int esirisc_jtag_break(struct esirisc_jtag *jtag_info);
|
||||
int esirisc_jtag_continue(struct esirisc_jtag *jtag_info);
|
||||
|
||||
int esirisc_jtag_flush_caches(struct esirisc_jtag *jtag_info);
|
||||
|
||||
#endif /* OPENOCD_TARGET_ESIRISC_JTAG_H */
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2018 by Square, Inc. *
|
||||
* Steven Stallion <stallion@squareup.com> *
|
||||
* James Zhao <hjz@squareup.com> *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef OPENOCD_TARGET_ESIRISC_REGS_H
|
||||
#define OPENOCD_TARGET_ESIRISC_REGS_H
|
||||
|
||||
enum esirisc_reg_num {
|
||||
ESIRISC_SP,
|
||||
ESIRISC_RA,
|
||||
ESIRISC_R2,
|
||||
ESIRISC_R3,
|
||||
ESIRISC_R4,
|
||||
ESIRISC_R5,
|
||||
ESIRISC_R6,
|
||||
ESIRISC_R7,
|
||||
ESIRISC_R8,
|
||||
ESIRISC_R9,
|
||||
ESIRISC_R10,
|
||||
ESIRISC_R11,
|
||||
ESIRISC_R12,
|
||||
ESIRISC_R13,
|
||||
ESIRISC_R14,
|
||||
ESIRISC_R15,
|
||||
ESIRISC_R16,
|
||||
ESIRISC_R17,
|
||||
ESIRISC_R18,
|
||||
ESIRISC_R19,
|
||||
ESIRISC_R20,
|
||||
ESIRISC_R21,
|
||||
ESIRISC_R22,
|
||||
ESIRISC_R23,
|
||||
ESIRISC_R24,
|
||||
ESIRISC_R25,
|
||||
ESIRISC_R26,
|
||||
ESIRISC_R27,
|
||||
ESIRISC_R28,
|
||||
ESIRISC_R29,
|
||||
ESIRISC_R30,
|
||||
ESIRISC_R31,
|
||||
|
||||
ESIRISC_V0,
|
||||
ESIRISC_V1,
|
||||
ESIRISC_V2,
|
||||
ESIRISC_V3,
|
||||
ESIRISC_V4,
|
||||
ESIRISC_V5,
|
||||
ESIRISC_V6,
|
||||
ESIRISC_V7,
|
||||
ESIRISC_V8,
|
||||
ESIRISC_V9,
|
||||
ESIRISC_V10,
|
||||
ESIRISC_V11,
|
||||
ESIRISC_V12,
|
||||
ESIRISC_V13,
|
||||
ESIRISC_V14,
|
||||
ESIRISC_V15,
|
||||
ESIRISC_V16,
|
||||
ESIRISC_V17,
|
||||
ESIRISC_V18,
|
||||
ESIRISC_V19,
|
||||
ESIRISC_V20,
|
||||
ESIRISC_V21,
|
||||
ESIRISC_V22,
|
||||
ESIRISC_V23,
|
||||
ESIRISC_V24,
|
||||
ESIRISC_V25,
|
||||
ESIRISC_V26,
|
||||
ESIRISC_V27,
|
||||
ESIRISC_V28,
|
||||
ESIRISC_V29,
|
||||
ESIRISC_V30,
|
||||
ESIRISC_V31,
|
||||
|
||||
ESIRISC_A0,
|
||||
ESIRISC_A1,
|
||||
ESIRISC_A2,
|
||||
ESIRISC_A3,
|
||||
ESIRISC_A4,
|
||||
ESIRISC_A5,
|
||||
ESIRISC_A6,
|
||||
ESIRISC_A7,
|
||||
|
||||
ESIRISC_PC,
|
||||
ESIRISC_CAS,
|
||||
ESIRISC_TC,
|
||||
ESIRISC_ETA,
|
||||
ESIRISC_ETC,
|
||||
ESIRISC_EPC,
|
||||
ESIRISC_ECAS,
|
||||
ESIRISC_EID,
|
||||
ESIRISC_ED,
|
||||
ESIRISC_IP,
|
||||
ESIRISC_IM,
|
||||
ESIRISC_IS,
|
||||
ESIRISC_IT,
|
||||
|
||||
ESIRISC_NUM_REGS,
|
||||
};
|
||||
|
||||
/* CSR Banks */
|
||||
#define CSR_THREAD 0x00
|
||||
#define CSR_INTERRUPT 0x01
|
||||
#define CSR_DEBUG 0x04
|
||||
#define CSR_CONFIG 0x05
|
||||
#define CSR_TRACE 0x09
|
||||
|
||||
/* Thread CSRs */
|
||||
#define CSR_THREAD_TC 0x00 /* Thread Control */
|
||||
#define CSR_THREAD_PC 0x01 /* Program Counter */
|
||||
#define CSR_THREAD_CAS 0x02 /* Comparison & Arithmetic Status */
|
||||
#define CSR_THREAD_AC 0x03 /* Arithmetic Control */
|
||||
#define CSR_THREAD_LF 0x04 /* Locked Flag */
|
||||
#define CSR_THREAD_LA 0x05 /* Locked Address */
|
||||
#define CSR_THREAD_ETA 0x07 /* Exception Table Address */
|
||||
#define CSR_THREAD_ETC 0x08 /* Exception TC */
|
||||
#define CSR_THREAD_EPC 0x09 /* Exception PC */
|
||||
#define CSR_THREAD_ECAS 0x0a /* Exception CAS */
|
||||
#define CSR_THREAD_EID 0x0b /* Exception ID */
|
||||
#define CSR_THREAD_ED 0x0c /* Exception Data */
|
||||
|
||||
/* Interrupt CSRs */
|
||||
#define CSR_INTERRUPT_IP 0x00 /* Interrupt Pending */
|
||||
#define CSR_INTERRUPT_IA 0x01 /* Interrupt Acknowledge */
|
||||
#define CSR_INTERRUPT_IM 0x02 /* Interrupt Mask */
|
||||
#define CSR_INTERRUPT_IS 0x03 /* Interrupt Sense */
|
||||
#define CSR_INTERRUPT_IT 0x04 /* Interrupt Trigger */
|
||||
|
||||
/* Debug CSRs */
|
||||
#define CSR_DEBUG_DC 0x00 /* Debug Control */
|
||||
#define CSR_DEBUG_IBC 0x01 /* Instruction Breakpoint Control */
|
||||
#define CSR_DEBUG_DBC 0x02 /* Data Breakpoint Control */
|
||||
#define CSR_DEBUG_HWDC 0x03 /* Hardware Debug Control */
|
||||
#define CSR_DEBUG_DBS 0x04 /* Data Breakpoint Size */
|
||||
#define CSR_DEBUG_DBR 0x05 /* Data Breakpoint Range */
|
||||
#define CSR_DEBUG_IBAn 0x08 /* Instruction Breakpoint Address [0..7] */
|
||||
#define CSR_DEBUG_DBAn 0x10 /* Data Breakpoint Address [0..7] */
|
||||
|
||||
/* Configuration CSRs */
|
||||
#define CSR_CONFIG_ARCH0 0x00 /* Architectural Configuration 0 */
|
||||
#define CSR_CONFIG_ARCH1 0x01 /* Architectural Configuration 1 */
|
||||
#define CSR_CONFIG_ARCH2 0x02 /* Architectural Configuration 2 */
|
||||
#define CSR_CONFIG_ARCH3 0x03 /* Architectural Configuration 3 */
|
||||
#define CSR_CONFIG_MEM 0x04 /* Memory Configuration */
|
||||
#define CSR_CONFIG_IC 0x05 /* Instruction Cache Configuration */
|
||||
#define CSR_CONFIG_DC 0x06 /* Data Cache Configuration */
|
||||
#define CSR_CONFIG_INT 0x07 /* Interrupt Configuration */
|
||||
#define CSR_CONFIG_ISAn 0x08 /* Instruction Set Configuration [0..6] */
|
||||
#define CSR_CONFIG_DBG 0x0f /* Debug Configuration */
|
||||
#define CSR_CONFIG_MID 0x10 /* Manufacturer ID */
|
||||
#define CSR_CONFIG_REV 0x11 /* Revision Number */
|
||||
#define CSR_CONFIG_MPID 0x12 /* Mulitprocessor ID */
|
||||
#define CSR_CONFIG_FREQn 0x13 /* Frequency [0..2] */
|
||||
#define CSR_CONFIG_TRACE 0x16 /* Trace Configuration */
|
||||
|
||||
/* Trace CSRs */
|
||||
#define CSR_TRACE_CONTROL 0x00
|
||||
#define CSR_TRACE_STATUS 0x01
|
||||
#define CSR_TRACE_BUFFER_START 0x02
|
||||
#define CSR_TRACE_BUFFER_END 0x03
|
||||
#define CSR_TRACE_BUFFER_CUR 0x04
|
||||
#define CSR_TRACE_TRIGGER 0x05
|
||||
#define CSR_TRACE_START_DATA 0x06
|
||||
#define CSR_TRACE_START_MASK 0x07
|
||||
#define CSR_TRACE_STOP_DATA 0x08
|
||||
#define CSR_TRACE_STOP_MASK 0x09
|
||||
#define CSR_TRACE_DELAY 0x0a
|
||||
|
||||
#endif /* OPENOCD_TARGET_ESIRISC_REGS_H */
|
||||
|
|
@ -109,6 +109,7 @@ extern struct target_type quark_d20xx_target;
|
|||
extern struct target_type stm8_target;
|
||||
extern struct target_type riscv_target;
|
||||
extern struct target_type mem_ap_target;
|
||||
extern struct target_type esirisc_target;
|
||||
|
||||
static struct target_type *target_types[] = {
|
||||
&arm7tdmi_target,
|
||||
|
|
@ -142,10 +143,11 @@ static struct target_type *target_types[] = {
|
|||
&quark_d20xx_target,
|
||||
&stm8_target,
|
||||
&riscv_target,
|
||||
&mem_ap_target,
|
||||
&esirisc_target,
|
||||
#if BUILD_TARGET64
|
||||
&aarch64_target,
|
||||
#endif
|
||||
&mem_ap_target,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -225,6 +225,13 @@ struct gdb_fileio_info {
|
|||
uint64_t param_4;
|
||||
};
|
||||
|
||||
/** Returns a description of the endianness for the specified target. */
|
||||
static inline const char *target_endianness(struct target *target)
|
||||
{
|
||||
return (target->endianness == TARGET_ENDIAN_UNKNOWN) ? "unknown" :
|
||||
(target->endianness == TARGET_BIG_ENDIAN) ? "big endian" : "little endian";
|
||||
}
|
||||
|
||||
/** Returns the instance-specific name of the specified target. */
|
||||
static inline const char *target_name(struct target *target)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
#
|
||||
# EnSilica eSi-32xx SoC (eSi-RISC Family)
|
||||
# http://www.ensilica.com/risc-ip/
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME esi32xx
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x11234001
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu
|
||||
|
||||
# Targets with the UNIFIED_ADDRESS_SPACE option disabled should set
|
||||
# CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed.
|
||||
if { [info exists CACHEARCH] } {
|
||||
$_TARGETNAME esirisc cache_arch $CACHEARCH
|
||||
}
|
||||
|
||||
adapter_khz 2000
|
||||
|
||||
reset_config none
|
||||
|
||||
# The default linker scripts provided by the eSi-RISC toolchain do not
|
||||
# specify attributes on memory regions, which results in incorrect
|
||||
# application of software breakpoints by GDB.
|
||||
gdb_breakpoint_override hard
|
||||
Loading…
Reference in New Issue