riscv: fix compile error

The commit b68674a1da ("Upstream tons of RISC-V changes.") was
proposed well before commit 3ac010bb9f ("Fix debug prints when
loading to flash"), but the merge got in different order.
After latest merge, the master branch fails to compile.

Fix the compile error.

Change-Id: Ia3bd21d970d589343a3b9b2d58c89e0c49f30015
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5856
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
This commit is contained in:
Antonio Borneo 2020-10-14 10:41:12 +02:00
parent b68674a1da
commit 4fc61a2f9d

View File

@ -3452,7 +3452,7 @@ static int register_get(struct reg *reg)
buf_set_u64(reg->value, 0, reg->size, value);
}
reg->valid = gdb_regno_cacheable(reg->number, false);
char *str = buf_to_str(reg->value, reg->size, 16);
char *str = buf_to_hex_str(reg->value, reg->size);
LOG_DEBUG("[%d]{%d} read 0x%s from %s (valid=%d)", target->coreid,
riscv_current_hartid(target), str, reg->name, reg->valid);
free(str);
@ -3465,7 +3465,7 @@ static int register_set(struct reg *reg, uint8_t *buf)
struct target *target = reg_info->target;
RISCV_INFO(r);
char *str = buf_to_str(buf, reg->size, 16);
char *str = buf_to_hex_str(buf, reg->size);
LOG_DEBUG("[%d]{%d} write 0x%s to %s (valid=%d)", target->coreid,
riscv_current_hartid(target), str, reg->name, reg->valid);
free(str);