diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c
index c5ec15289..a001811c8 100644
--- a/src/flash/nor/at91sam4l.c
+++ b/src/flash/nor/at91sam4l.c
@@ -660,14 +660,14 @@ COMMAND_HANDLER(sam4l_handle_reset_deassert)
 	 * After vectreset SMAP release is not needed however makes no harm
 	 */
 	if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
-		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
 		if (retval == ERROR_OK)
-			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
+			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
 				TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 		/* do not return on error here, releasing SMAP reset is more important */
 	}
 
-	int retval2 = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, SMAP_SCR, SMAP_SCR_HCR);
+	int retval2 = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, SMAP_SCR, SMAP_SCR_HCR);
 	if (retval2 != ERROR_OK)
 		return retval2;
 
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index 6e37dd332..f3f6b2836 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -1000,9 +1000,9 @@ COMMAND_HANDLER(samd_handle_reset_deassert)
 	 * After vectreset DSU release is not needed however makes no harm
 	 */
 	if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
-		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
 		if (retval == ERROR_OK)
-			retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
+			retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
 				TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 		/* do not return on error here, releasing DSU reset is more important */
 	}
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 3a81784e3..fad47c327 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -804,16 +804,16 @@ static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t
 /*
  * This function checks the ID for each access port to find the requested Access Port type
  */
-int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
+int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 {
-	int ap;
+	int ap_num;
 
 	/* Maximum AP number is 255 since the SELECT register is 8 bits */
-	for (ap = 0; ap <= 255; ap++) {
+	for (ap_num = 0; ap_num <= 255; ap_num++) {
 
 		/* read the IDR register of the Access Port */
 		uint32_t id_val = 0;
-		dap_ap_select(dap, ap);
+		dap_ap_select(dap, ap_num);
 
 		int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 		if (retval != ERROR_OK)
@@ -843,9 +843,9 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_nu
 						(type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 						(type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 						(type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
-						ap, id_val);
+						ap_num, id_val);
 
-			*ap_num_out = ap;
+			*ap_out = &dap->ap[ap_num];
 			return ERROR_OK;
 		}
 	}
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 85b622430..224cf712e 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -480,7 +480,7 @@ int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 /* Probe Access Ports to find a particular type */
 int dap_find_ap(struct adiv5_dap *dap,
 			enum ap_type type_to_find,
-			uint8_t *ap_num_out);
+			struct adiv5_ap **ap_out);
 
 /* Lookup CoreSight component */
 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index cb7eb01ff..5ca4eb86e 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -107,8 +107,8 @@ struct armv7a_common {
 	/* Core Debug Unit */
 	struct arm_dpm dpm;
 	uint32_t debug_base;
-	uint8_t debug_ap;
-	uint8_t memory_ap;
+	struct adiv5_ap *debug_ap;
+	struct adiv5_ap *memory_ap;
 	bool memory_ap_available;
 	/* mdir */
 	uint8_t multi_processor_system;
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index a012fa23f..65a2ef059 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -148,7 +148,7 @@ struct armv7m_common {
 	int exception_number;
 
 	/* AP this processor is connected to in the DAP */
-	uint8_t debug_ap;
+	struct adiv5_ap *debug_ap;
 
 	int fp_feature;
 	uint32_t demcr;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index a65cabf5a..61e098956 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -195,11 +195,11 @@ static int cortex_a8_init_debug_access(struct target *target)
 
 	/* Unlocking the debug registers for modification
 	 * The debugport might be uninitialised so try twice */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
 	if (retval != ERROR_OK) {
 		/* try again */
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
 		if (retval == ERROR_OK)
 			LOG_USER(
@@ -228,7 +228,7 @@ static int cortex_a_init_debug_access(struct target *target)
 	switch (cortex_part_num) {
 	case CORTEX_A7_PARTNUM:
 	case CORTEX_A15_PARTNUM:
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 						    armv7a->debug_base + CPUDBG_OSLSR,
 						    &dbg_osreg);
 		if (retval != ERROR_OK)
@@ -238,7 +238,7 @@ static int cortex_a_init_debug_access(struct target *target)
 
 		if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
 			/* Unlocking the DEBUG OS registers for modification */
-			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 							     armv7a->debug_base + CPUDBG_OSLAR,
 							     0);
 		break;
@@ -254,7 +254,7 @@ static int cortex_a_init_debug_access(struct target *target)
 		return retval;
 	/* Clear Sticky Power Down status Bit in PRSR to enable access to
 	   the registers in the Core Power Domain */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
 	LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR  0x%" PRIx32, target->coreid, dbg_osreg);
 
@@ -262,13 +262,13 @@ static int cortex_a_init_debug_access(struct target *target)
 		return retval;
 
 	/* Disable cacheline fills and force cache write-through in debug state */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCCR, 0);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Disable TLB lookup and refill/eviction in debug state */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSMCR, 0);
 	if (retval != ERROR_OK)
 		return retval;
@@ -291,7 +291,7 @@ static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool f
 	long long then = timeval_ms();
 	while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
 		force = false;
-		int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DSCR, dscr);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Could not read DSCR register");
@@ -327,14 +327,14 @@ static int cortex_a_exec_opcode(struct target *target,
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_ITR, opcode);
 	if (retval != ERROR_OK)
 		return retval;
 
 	long long then = timeval_ms();
 	do {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Could not read DSCR register");
@@ -373,7 +373,7 @@ static int cortex_a_read_regs_through_mem(struct target *target, uint32_t addres
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap,
+	retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap->ap_num,
 			(uint8_t *)(&regfile[1]), 4, 15, address);
 
 	return retval;
@@ -425,7 +425,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
 	/* Wait for DTRRXfull then read DTRRTX */
 	long long then = timeval_ms();
 	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
@@ -435,7 +435,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
 		}
 	}
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DTRTX, value);
 	LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
 
@@ -454,7 +454,7 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
 	LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
 
 	/* Check that DCCRX is not full */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -472,7 +472,7 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
 
 	/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
 	LOG_DEBUG("write DCC 0x%08" PRIx32, value);
-	retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DTRRX, value);
 	if (retval != ERROR_OK)
 		return retval;
@@ -530,7 +530,7 @@ static int cortex_a_dap_write_memap_register_u32(struct target *target,
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct adiv5_dap *swjdp = armv7a->arm.dap;
 
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, address, value);
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num, address, value);
 
 	return retval;
 }
@@ -555,7 +555,7 @@ static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
 {
 	LOG_DEBUG("write DCC 0x%08" PRIx32, data);
 	return mem_ap_sel_write_u32(a->armv7a_common.arm.dap,
-		a->armv7a_common.debug_ap, a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+		a->armv7a_common.debug_ap->ap_num, a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
 }
 
 static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
@@ -571,7 +571,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
 	/* Wait for DTRRXfull */
 	long long then = timeval_ms();
 	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
 				a->armv7a_common.debug_base + CPUDBG_DSCR,
 				&dscr);
 		if (retval != ERROR_OK)
@@ -582,7 +582,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
 		}
 	}
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
 			a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
 	if (retval != ERROR_OK)
 		return retval;
@@ -604,7 +604,7 @@ static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
 	/* set up invariant:  INSTR_COMP is set after ever DPM operation */
 	long long then = timeval_ms();
 	for (;; ) {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
 				a->armv7a_common.debug_base + CPUDBG_DSCR,
 				&dscr);
 		if (retval != ERROR_OK)
@@ -892,7 +892,7 @@ static int cortex_a_poll(struct target *target)
 		target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		return retval;
 	}
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -954,7 +954,7 @@ static int cortex_a_halt(struct target *target)
 	 * Tell the core to be halted by writing DRCR with 0x1
 	 * and then wait for the core to be halted.
 	 */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
 	if (retval != ERROR_OK)
 		return retval;
@@ -962,19 +962,19 @@ static int cortex_a_halt(struct target *target)
 	/*
 	 * enter halting debug mode
 	 */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
 	if (retval != ERROR_OK)
 		return retval;
 
 	long long then = timeval_ms();
 	for (;; ) {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1100,7 +1100,7 @@ static int cortex_a_internal_restart(struct target *target)
 	 * disable IRQs by default, with optional override...
 	 */
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1108,12 +1108,12 @@ static int cortex_a_internal_restart(struct target *target)
 	if ((dscr & DSCR_INSTR_COMP) == 0)
 		LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
 
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
 			DRCR_CLEAR_EXCEPTIONS);
 	if (retval != ERROR_OK)
@@ -1121,7 +1121,7 @@ static int cortex_a_internal_restart(struct target *target)
 
 	long long then = timeval_ms();
 	for (;; ) {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1213,7 +1213,7 @@ static int cortex_a_debug_entry(struct target *target)
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
 
 	/* REVISIT surely we should not re-read DSCR !! */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1225,7 +1225,7 @@ static int cortex_a_debug_entry(struct target *target)
 
 	/* Enable the ITR execution once we are in debug mode */
 	dscr |= DSCR_ITR_EN;
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1237,7 +1237,7 @@ static int cortex_a_debug_entry(struct target *target)
 	if (target->debug_reason == DBG_REASON_WATCHPOINT) {
 		uint32_t wfar;
 
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_WFAR,
 				&wfar);
 		if (retval != ERROR_OK)
@@ -1360,7 +1360,7 @@ int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsign
 	uint32_t dscr;
 
 	/* Read DSCR */
-	int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (ERROR_OK != retval)
 		return retval;
@@ -1371,7 +1371,7 @@ int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsign
 	dscr |= value & bit_mask;
 
 	/* write new DSCR */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
 	return retval;
 }
@@ -1953,7 +1953,7 @@ static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t
 	if (new_dscr != *dscr) {
 		struct armv7a_common *armv7a = target_to_armv7a(target);
 		int retval = mem_ap_sel_write_atomic_u32(armv7a->arm.dap,
-				armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, new_dscr);
+				armv7a->debug_ap->ap_num, armv7a->debug_base + CPUDBG_DSCR, new_dscr);
 		if (retval == ERROR_OK)
 			*dscr = new_dscr;
 		return retval;
@@ -1972,7 +1972,7 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 	int retval;
 
 	while ((*dscr & mask) != value) {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DSCR, dscr);
 		if (retval != ERROR_OK)
 			return retval;
@@ -2011,7 +2011,7 @@ static int cortex_a_read_copro(struct target *target, uint32_t opcode,
 		return retval;
 
 	/* Read the value transferred to DTRTX. */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DTRTX, data);
 	if (retval != ERROR_OK)
 		return retval;
@@ -2047,7 +2047,7 @@ static int cortex_a_write_copro(struct target *target, uint32_t opcode,
 	struct adiv5_dap *swjdp = armv7a->arm.dap;
 
 	/* Write the value into DTRRX. */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DTRRX, data);
 	if (retval != ERROR_OK)
 		return retval;
@@ -2151,7 +2151,7 @@ static int cortex_a_write_apb_ab_memory_slow(struct target *target,
 			data = target_buffer_get_u16(target, buffer);
 		else
 			data = target_buffer_get_u32(target, buffer);
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DTRRX, data);
 		if (retval != ERROR_OK)
 			return retval;
@@ -2212,13 +2212,13 @@ static int cortex_a_write_apb_ab_memory_fast(struct target *target,
 		return retval;
 
 	/* Latch STC instruction. */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Transfer all the data and issue all the instructions. */
-	return mem_ap_sel_write_buf_noincr(swjdp, armv7a->debug_ap, buffer,
+	return mem_ap_sel_write_buf_noincr(swjdp, armv7a->debug_ap->ap_num, buffer,
 			4, count, armv7a->debug_base + CPUDBG_DTRRX);
 }
 
@@ -2244,13 +2244,13 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
 		return ERROR_OK;
 
 	/* Clear any abort. */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Read DSCR. */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -2269,7 +2269,7 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
 		goto out;
 
 	/* Get the memory address into R0. */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DTRRX, address);
 	if (retval != ERROR_OK)
 		goto out;
@@ -2313,7 +2313,7 @@ out:
 	/* If there were any sticky abort flags, clear them. */
 	if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
 		fault_dscr = dscr;
-		mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+		mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
 		dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
 	} else {
@@ -2347,7 +2347,7 @@ out:
 	/* If the DCC is nonempty, clear it. */
 	if (dscr & DSCR_DTRTX_FULL_LATCHED) {
 		uint32_t dummy;
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DTRTX, &dummy);
 		if (final_retval == ERROR_OK)
 			final_retval = retval;
@@ -2420,7 +2420,7 @@ static int cortex_a_read_apb_ab_memory_slow(struct target *target,
 			return retval;
 
 		/* Read the value transferred to DTRTX into the buffer. */
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DTRTX, &data);
 		if (retval != ERROR_OK)
 			return retval;
@@ -2473,7 +2473,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
 			return retval;
 
 		/* Latch LDC instruction. */
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
 		if (retval != ERROR_OK)
 			return retval;
@@ -2484,7 +2484,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
 		 * memory. The last read of DTRTX in this call reads the second-to-last
 		 * word from memory and issues the read instruction for the last word.
 		 */
-		retval = mem_ap_sel_read_buf_noincr(swjdp, armv7a->debug_ap, buffer,
+		retval = mem_ap_sel_read_buf_noincr(swjdp, armv7a->debug_ap->ap_num, buffer,
 				4, count, armv7a->debug_base + CPUDBG_DTRTX);
 		if (retval != ERROR_OK)
 			return retval;
@@ -2518,7 +2518,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
 
 	/* Read the value transferred to DTRTX into the buffer. This is the last
 	 * word. */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DTRTX, &u32);
 	if (retval != ERROR_OK)
 		return retval;
@@ -2549,13 +2549,13 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
 		return ERROR_OK;
 
 	/* Clear any abort. */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Read DSCR */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -2574,7 +2574,7 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
 		goto out;
 
 	/* Get the memory address into R0. */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DTRRX, address);
 	if (retval != ERROR_OK)
 		goto out;
@@ -2606,7 +2606,7 @@ out:
 	/* If there were any sticky abort flags, clear them. */
 	if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
 		fault_dscr = dscr;
-		mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+		mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
 		dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
 	} else {
@@ -2640,7 +2640,7 @@ out:
 	/* If the DCC is nonempty, clear it. */
 	if (dscr & DSCR_DTRTX_FULL_LATCHED) {
 		uint32_t dummy;
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DTRTX, &dummy);
 		if (final_retval == ERROR_OK)
 			final_retval = retval;
@@ -2707,7 +2707,7 @@ static int cortex_a_read_memory_ahb(struct target *target, uint32_t address,
 	struct adiv5_dap *swjdp = armv7a->arm.dap;
 	uint8_t apsel = swjdp->apsel;
 
-	if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap))
+	if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap->ap_num))
 		return target_read_memory(target, address, size, count, buffer);
 
 	/* cortex_a handles unaligned memory access */
@@ -2735,7 +2735,7 @@ static int cortex_a_read_memory_ahb(struct target *target, uint32_t address,
 	if (!count || !buffer)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
+	retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap->ap_num, buffer, size, count, address);
 
 	return retval;
 }
@@ -2787,7 +2787,7 @@ static int cortex_a_write_memory_ahb(struct target *target, uint32_t address,
 	struct adiv5_dap *swjdp = armv7a->arm.dap;
 	uint8_t apsel = swjdp->apsel;
 
-	if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap))
+	if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap->ap_num))
 		return target_write_memory(target, address, size, count, buffer);
 
 	/* cortex_a handles unaligned memory access */
@@ -2816,7 +2816,7 @@ static int cortex_a_write_memory_ahb(struct target *target, uint32_t address,
 	if (!count || !buffer)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
+	retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap->ap_num, buffer, size, count, address);
 
 	return retval;
 }
@@ -2904,16 +2904,16 @@ static int cortex_a_handle_target_request(void *priv)
 	if (target->state == TARGET_RUNNING) {
 		uint32_t request;
 		uint32_t dscr;
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 
 		/* check if we have data */
 		while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
-			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 					armv7a->debug_base + CPUDBG_DTRTX, &request);
 			if (retval == ERROR_OK) {
 				target_request(target, request);
-				retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+				retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 						armv7a->debug_base + CPUDBG_DSCR, &dscr);
 			}
 		}
@@ -2945,7 +2945,7 @@ static int cortex_a_examine_first(struct target *target)
 	/* We do one extra read to ensure DAP is configured,
 	 * we call ahbap_debugport_init(swjdp) instead
 	 */
-	retval = ahbap_debugport_init(swjdp, armv7a->debug_ap);
+	retval = ahbap_debugport_init(swjdp, armv7a->debug_ap->ap_num);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -2983,33 +2983,33 @@ static int cortex_a_examine_first(struct target *target)
 	} else
 		armv7a->debug_base = target->dbgbase;
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_CPUID, &cpuid);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_CPUID, &cpuid);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("Examine %s failed", "CPUID");
 		return retval;
 	}
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_CTYPR, &ctypr);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("Examine %s failed", "CTYPR");
 		return retval;
 	}
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_TTYPR, &ttypr);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("Examine %s failed", "TTYPR");
 		return retval;
 	}
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 			armv7a->debug_base + CPUDBG_DIDR, &didr);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("Examine %s failed", "DIDR");
@@ -3030,7 +3030,7 @@ static int cortex_a_examine_first(struct target *target)
 	if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
 		CORTEX_A15_PARTNUM) {
 
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 						     armv7a->debug_base + CPUDBG_OSLAR,
 						     0);
 
@@ -3042,7 +3042,7 @@ static int cortex_a_examine_first(struct target *target)
 	if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
 		CORTEX_A7_PARTNUM) {
 
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 						     armv7a->debug_base + CPUDBG_OSLAR,
 						     0);
 
@@ -3050,7 +3050,7 @@ static int cortex_a_examine_first(struct target *target)
 			return retval;
 
 	}
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
 					    armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
 
 	if (retval != ERROR_OK)
@@ -3209,7 +3209,7 @@ static int cortex_a_virt2phys(struct target *target,
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct adiv5_dap *swjdp = armv7a->arm.dap;
 	uint8_t apsel = swjdp->apsel;
-	if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
+	if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num)) {
 		uint32_t ret;
 		retval = armv7a_mmu_translate_va(target,
 				virt, &ret);
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 7a7194a11..7999e3836 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -74,16 +74,16 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
 	/* because the DCB_DCRDR is used for the emulated dcc channel
 	 * we have to save/restore the DCB_DCRDR when used */
 	if (target->dbg_msg_enabled) {
-		retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, &dcrdr);
+		retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, &dcrdr);
 		if (retval != ERROR_OK)
 			return retval;
 	}
 
-	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRSR, regnum);
+	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRSR, regnum);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, value);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, value);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -91,7 +91,7 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
 		/* restore DCB_DCRDR - this needs to be in a separate
 		 * transaction otherwise the emulated DCC channel breaks */
 		if (retval == ERROR_OK)
-			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, dcrdr);
+			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, dcrdr);
 	}
 
 	return retval;
@@ -108,16 +108,16 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
 	/* because the DCB_DCRDR is used for the emulated dcc channel
 	 * we have to save/restore the DCB_DCRDR when used */
 	if (target->dbg_msg_enabled) {
-		retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, &dcrdr);
+		retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, &dcrdr);
 		if (retval != ERROR_OK)
 			return retval;
 	}
 
-	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, value);
+	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, value);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRSR, regnum | DCRSR_WnR);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -125,7 +125,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
 		/* restore DCB_DCRDR - this needs to be in a seperate
 		 * transaction otherwise the emulated DCC channel breaks */
 		if (retval == ERROR_OK)
-			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, dcrdr);
+			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, dcrdr);
 	}
 
 	return retval;
@@ -143,7 +143,7 @@ static int cortex_m_write_debug_halt_mask(struct target *target,
 	/* create new register mask */
 	cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 
-	return mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
+	return mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, cortex_m->dcb_dhcsr);
 }
 
 static int cortex_m_clear_halt(struct target *target)
@@ -157,12 +157,12 @@ static int cortex_m_clear_halt(struct target *target)
 	cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 
 	/* Read Debug Fault Status Register */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR, &cortex_m->nvic_dfsr);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Clear Debug Fault Status */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR, cortex_m->nvic_dfsr);
 	if (retval != ERROR_OK)
 		return retval;
 	LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
@@ -186,12 +186,12 @@ static int cortex_m_single_step_core(struct target *target)
 	 * HALT can put the core into an unknown state.
 	 */
 	if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR,
 				DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 		if (retval != ERROR_OK)
 			return retval;
 	}
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR,
 			DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 	if (retval != ERROR_OK)
 		return retval;
@@ -234,22 +234,22 @@ static int cortex_m_endreset_event(struct target *target)
 	struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 
 	/* REVISIT The four debug monitor bits are currently ignored... */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, &dcb_demcr);
 	if (retval != ERROR_OK)
 		return retval;
 	LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 
 	/* this register is used for emulated dcc channel */
-	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, 0);
+	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, 0);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Enable debug requests */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 	if (retval != ERROR_OK)
 		return retval;
 	if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
-		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 		if (retval != ERROR_OK)
 			return retval;
 	}
@@ -264,7 +264,7 @@ static int cortex_m_endreset_event(struct target *target)
 	 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 	 * or manual updates to the NVIC SHCSR and CCR registers.
 	 */
-	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
+	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, TRCENA | armv7m->demcr);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -310,7 +310,7 @@ static int cortex_m_endreset_event(struct target *target)
 	register_cache_invalidate(armv7m->arm.core_cache);
 
 	/* make sure we have latest dhcsr flags */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 
 	return retval;
 }
@@ -346,47 +346,47 @@ static int cortex_m_examine_exception_reason(struct target *target)
 	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	int retval;
 
-	retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_SHCSR, &shcsr);
+	retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_SHCSR, &shcsr);
 	if (retval != ERROR_OK)
 		return retval;
 	switch (armv7m->exception_number) {
 		case 2:	/* NMI */
 			break;
 		case 3:	/* Hard Fault */
-			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_HFSR, &except_sr);
+			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_HFSR, &except_sr);
 			if (retval != ERROR_OK)
 				return retval;
 			if (except_sr & 0x40000000) {
-				retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &cfsr);
+				retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &cfsr);
 				if (retval != ERROR_OK)
 					return retval;
 			}
 			break;
 		case 4:	/* Memory Management */
-			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
+			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &except_sr);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_MMFAR, &except_ar);
+			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_MMFAR, &except_ar);
 			if (retval != ERROR_OK)
 				return retval;
 			break;
 		case 5:	/* Bus Fault */
-			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
+			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &except_sr);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_BFAR, &except_ar);
+			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_BFAR, &except_ar);
 			if (retval != ERROR_OK)
 				return retval;
 			break;
 		case 6:	/* Usage Fault */
-			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
+			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &except_sr);
 			if (retval != ERROR_OK)
 				return retval;
 			break;
 		case 11:	/* SVCall */
 			break;
 		case 12:	/* Debug Monitor */
-			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, &except_sr);
+			retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR, &except_sr);
 			if (retval != ERROR_OK)
 				return retval;
 			break;
@@ -421,7 +421,7 @@ static int cortex_m_debug_entry(struct target *target)
 	LOG_DEBUG(" ");
 
 	cortex_m_clear_halt(target);
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -499,7 +499,7 @@ static int cortex_m_poll(struct target *target)
 	struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 
 	/* Read from Debug Halting Control and Status Register */
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 	if (retval != ERROR_OK) {
 		target->state = TARGET_UNKNOWN;
 		return retval;
@@ -520,7 +520,7 @@ static int cortex_m_poll(struct target *target)
 		detected_failure = ERROR_FAIL;
 
 		/* refresh status bits */
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 		if (retval != ERROR_OK)
 			return retval;
 	}
@@ -636,13 +636,13 @@ static int cortex_m_soft_reset_halt(struct target *target)
 	LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
 
 	/* Enter debug state on reset; restore DEMCR in endreset_event() */
-	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
+	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
 			TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* Request a core-only reset */
-	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR,
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_AIRCR,
 			AIRCR_VECTKEY | AIRCR_VECTRESET);
 	if (retval != ERROR_OK)
 		return retval;
@@ -652,9 +652,9 @@ static int cortex_m_soft_reset_halt(struct target *target)
 	register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 
 	while (timeout < 100) {
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &dcb_dhcsr);
 		if (retval == ERROR_OK) {
-			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR,
+			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR,
 					&cortex_m->nvic_dfsr);
 			if (retval != ERROR_OK)
 				return retval;
@@ -898,7 +898,7 @@ static int cortex_m_step(struct target *target, int current,
 
 					/* Wait for pending handlers to complete or timeout */
 					do {
-						retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap,
+						retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num,
 								DCB_DHCSR,
 								&cortex_m->dcb_dhcsr);
 						if (retval != ERROR_OK) {
@@ -933,7 +933,7 @@ static int cortex_m_step(struct target *target, int current,
 		}
 	}
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -1001,11 +1001,11 @@ static int cortex_m_assert_reset(struct target *target)
 
 	/* Enable debug requests */
 	int retval;
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 	if (retval != ERROR_OK)
 		return retval;
 	if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
-		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 		if (retval != ERROR_OK)
 			return retval;
 	}
@@ -1013,19 +1013,19 @@ static int cortex_m_assert_reset(struct target *target)
 	/* If the processor is sleeping in a WFI or WFE instruction, the
 	 * C_HALT bit must be asserted to regain control */
 	if (cortex_m->dcb_dhcsr & S_SLEEP) {
-		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
 		if (retval != ERROR_OK)
 			return retval;
 	}
 
-	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, 0);
+	retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, 0);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (!target->reset_halt) {
 		/* Set/Clear C_MASKINTS in a separate operation */
 		if (cortex_m->dcb_dhcsr & C_MASKINTS) {
-			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
+			retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR,
 					DBGKEY | C_DEBUGEN | C_HALT);
 			if (retval != ERROR_OK)
 				return retval;
@@ -1043,7 +1043,7 @@ static int cortex_m_assert_reset(struct target *target)
 		 * bad vector table entries.  Should this include MMERR or
 		 * other flags too?
 		 */
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
 				TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1067,13 +1067,13 @@ static int cortex_m_assert_reset(struct target *target)
 				"handler to reset any peripherals or configure hardware srst support.");
 		}
 
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR,
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_AIRCR,
 				AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
 				? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
 		if (retval != ERROR_OK)
 			LOG_DEBUG("Ignoring AP write error right after reset");
 
-		retval = ahbap_debugport_init(swjdp, armv7m->debug_ap);
+		retval = ahbap_debugport_init(swjdp, armv7m->debug_ap->ap_num);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("DP initialisation failed");
 			return retval;
@@ -1085,7 +1085,7 @@ static int cortex_m_assert_reset(struct target *target)
 			 * after reset) on LM3S6918 -- Michael Schwingen
 			 */
 			uint32_t tmp;
-			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR, &tmp);
+			retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_AIRCR, &tmp);
 			if (retval != ERROR_OK)
 				return retval;
 		}
@@ -1119,7 +1119,7 @@ static int cortex_m_deassert_reset(struct target *target)
 
 	if ((jtag_reset_config & RESET_HAS_SRST) &&
 	    !(jtag_reset_config & RESET_SRST_NO_GATING)) {
-		int retval = ahbap_debugport_init(armv7m->arm.dap, armv7m->debug_ap);
+		int retval = ahbap_debugport_init(armv7m->arm.dap, armv7m->debug_ap->ap_num);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("DP initialisation failed");
 			return retval;
@@ -1680,7 +1680,7 @@ static int cortex_m_read_memory(struct target *target, uint32_t address,
 			return ERROR_TARGET_UNALIGNED_ACCESS;
 	}
 
-	return mem_ap_sel_read_buf(swjdp, armv7m->debug_ap, buffer, size, count, address);
+	return mem_ap_sel_read_buf(swjdp, armv7m->debug_ap->ap_num, buffer, size, count, address);
 }
 
 static int cortex_m_write_memory(struct target *target, uint32_t address,
@@ -1695,7 +1695,7 @@ static int cortex_m_write_memory(struct target *target, uint32_t address,
 			return ERROR_TARGET_UNALIGNED_ACCESS;
 	}
 
-	return mem_ap_sel_write_buf(swjdp, armv7m->debug_ap, buffer, size, count, address);
+	return mem_ap_sel_write_buf(swjdp, armv7m->debug_ap->ap_num, buffer, size, count, address);
 }
 
 static int cortex_m_init_target(struct command_context *cmd_ctx,
@@ -1911,12 +1911,12 @@ int cortex_m_examine(struct target *target)
 	}
 
 	/* Leave (only) generic DAP stuff for debugport_init(); */
-	swjdp->ap[armv7m->debug_ap].memaccess_tck = 8;
+	armv7m->debug_ap->memaccess_tck = 8;
 
 	/* stlink shares the examine handler but does not support
 	 * all its calls */
 	if (!armv7m->stlink) {
-		retval = ahbap_debugport_init(swjdp, armv7m->debug_ap);
+		retval = ahbap_debugport_init(swjdp, armv7m->debug_ap->ap_num);
 		if (retval != ERROR_OK)
 			return retval;
 	}
@@ -1967,7 +1967,7 @@ int cortex_m_examine(struct target *target)
 
 		if (i == 4 || i == 3) {
 			/* Cortex-M3/M4 has 4096 bytes autoincrement range */
-			swjdp->ap[armv7m->debug_ap].tar_autoincr_block = (1 << 12);
+			armv7m->debug_ap->tar_autoincr_block = (1 << 12);
 		}
 
 		/* Configure trace modules */
@@ -2032,7 +2032,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
 	uint8_t buf[2];
 	int retval;
 
-	retval = mem_ap_sel_read_buf_noincr(swjdp, armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
+	retval = mem_ap_sel_read_buf_noincr(swjdp, armv7m->debug_ap->ap_num, buf, 2, 1, DCB_DCRDR);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -2046,7 +2046,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
 	 * signify we have read data */
 	if (dcrdr & (1 << 0)) {
 		target_buffer_set_u16(target, buf, 0);
-		retval = mem_ap_sel_write_buf_noincr(swjdp, armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
+		retval = mem_ap_sel_write_buf_noincr(swjdp, armv7m->debug_ap->ap_num, buf, 2, 1, DCB_DCRDR);
 		if (retval != ERROR_OK)
 			return retval;
 	}
@@ -2202,7 +2202,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &demcr);
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, &demcr);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -2239,10 +2239,10 @@ write:
 		demcr |= catch;
 
 		/* write, but don't assume it stuck (why not??) */
-		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, demcr);
+		retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, demcr);
 		if (retval != ERROR_OK)
 			return retval;
-		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &demcr);
+		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, &demcr);
 		if (retval != ERROR_OK)
 			return retval;