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ARM: rename armv4_5_state_* as arm_state_*

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And make arm_state_strings[] be const.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-12-04 19:39:25 -08:00
parent d4d16f1036
commit 56e0171420
12 changed files with 23 additions and 23 deletions
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2
src/target/arm720t.c
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@ -237,7 +237,7 @@ static int arm720t_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),

2
src/target/arm920t.c
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@ -451,7 +451,7 @@ int arm920t_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),

2
src/target/arm926ejs.c
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@ -507,7 +507,7 @@ int arm926ejs_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),

4
src/target/arm_simulator.c
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@ -824,14 +824,14 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
return buf_get_u32(armv4_5->cpsr->value, pos, bits);
}
static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
return armv4_5->core_state;
}
static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;

4
src/target/arm_simulator.h
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@ -32,8 +32,8 @@ struct arm_sim_interface
uint32_t (*get_reg_mode)(struct arm_sim_interface *sim, int reg);
void (*set_reg_mode)(struct arm_sim_interface *sim, int reg, uint32_t value);
uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
enum arm_state (*get_state)(struct arm_sim_interface *sim);
void (*set_state)(struct arm_sim_interface *sim, enum arm_state mode);
enum arm_mode (*get_mode)(struct arm_sim_interface *sim);
};

12
src/target/armv4_5.c
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@ -216,7 +216,7 @@ enum arm_mode armv4_5_number_to_mode(int number)
}
}
char* armv4_5_state_strings[] =
const char *arm_state_strings[] =
{
"ARM", "Thumb", "Jazelle", "ThumbEE",
};
@ -374,7 +374,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
: arm->core_cache->reg_list + arm->map[16];
/* Older ARMs won't have the J bit */
enum armv4_5_state state;
enum arm_state state;
if (cpsr & (1 << 5)) { /* T */
if (cpsr & (1 << 24)) { /* J */
@ -393,7 +393,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
arm_mode_name(mode),
armv4_5_state_strings[arm->core_state]);
arm_state_strings[arm->core_state]);
}
/**
@ -593,7 +593,7 @@ int armv4_5_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
armv4_5_state_strings[armv4_5->core_state],
arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
@ -718,7 +718,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
}
}
command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]);
return ERROR_OK;
}
@ -1038,7 +1038,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
{
struct arm *armv4_5 = target_to_armv4_5(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
enum arm_state core_state = armv4_5->core_state;
uint32_t context[17];
uint32_t cpsr;
int exit_breakpoint_size = 0;

10
src/target/armv4_5.h
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@ -49,15 +49,15 @@ bool is_arm_mode(unsigned psr_mode);
int arm_mode_to_number(enum arm_mode mode);
enum arm_mode armv4_5_number_to_mode(int number);
typedef enum armv4_5_state
typedef enum arm_state
{
ARM_STATE_ARM,
ARM_STATE_THUMB,
ARM_STATE_JAZELLE,
ARM_STATE_THUMB_EE,
} armv4_5_state_t;
} arm_state_t;
extern char* armv4_5_state_strings[];
extern const char *arm_state_strings[];
extern const int armv4_5_core_reg_map[8][17];
@ -98,7 +98,7 @@ struct arm
enum arm_mode core_type;
enum arm_mode core_mode;
enum armv4_5_state core_state;
enum arm_state core_state;
/** Flag reporting unavailability of the BKPT instruction. */
bool is_armv4;
@ -159,7 +159,7 @@ struct armv4_5_algorithm
int common_magic;
enum arm_mode core_mode;
enum armv4_5_state core_state;
enum arm_state core_state;
};
struct arm_reg

2
src/target/armv7a.h
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@ -119,7 +119,7 @@ struct armv7a_algorithm
int common_magic;
enum arm_mode core_mode;
enum armv4_5_state core_state;
enum arm_state core_state;
};
struct armv7a_core_reg

2
src/target/etm.h
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@ -164,7 +164,7 @@ struct etm_context
uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
etmv1_tracemode_t tracemode; /* type of info trace contains */
int /*armv4_5_state_t*/ core_state; /* current core state */
int /*arm_state_t*/ core_state; /* current core state */
struct image *image; /* source for target opcodes */
uint32_t pipe_index; /* current trace cycle */
uint32_t data_index; /* cycle holding next data packet */

2
src/target/feroceon.c
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@ -455,7 +455,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
int retval;
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
enum arm_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
uint32_t i;

2
src/target/xscale.c
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@ -867,7 +867,7 @@ static int xscale_arch_state(struct target *target)
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s"
"%s",
armv4_5_state_strings[armv4_5->core_state],
arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),

2
src/target/xscale.h
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@ -79,7 +79,7 @@ struct xscale_trace
int buffer_fill; /* maximum number of trace runs to read (-1 for wrap-around) */
int pc_ok;
uint32_t current_pc;
armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
arm_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
};
struct xscale_common