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flash/nor/stm32f1x: Add support for GD32E23x 

GD32E23x from GigaDevice is cortex-M23 microcontroller and it can work with the stm32f1x driver.
Modifications are similar to this done for GD32F1x0 in #6164 (https://review.openocd.org/c/openocd/+/6164).
Configuration file is added because its cortex-M23 CPU ID is different.
I think that GigaDevice microcontrollers should be handled in an independent unit to separate them from STM32,
but nowadays quick solution is welcome.

Signed-off-by: asier70Andrzej Sierżęga <asier70@gmail.com>
Change-Id: I91f31f5f66808bc50a8f607ac2c107e6b7c5e2b8
Reviewed-on: https://review.openocd.org/c/openocd/+/6527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
asier70 2021-09-01 22:00:51 +02:00 committed by Tomas Vanek
parent a498a3deaa
commit 5a0b4889d0
4 changed files with 96 additions and 4 deletions
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4
doc/openocd.texi
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@ -7120,8 +7120,8 @@ applied to all of them.
@deffn {Flash Driver} {stm32f1x}
All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
from STMicroelectronics and all members of the GD32F1x0 and GD32F3x0 microcontroller
families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4 cores.
from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.

19
src/flash/nor/stm32f1x.c
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@ -640,6 +640,9 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
case CORTEX_M4_PARTNO: /* STM32F3x devices */
device_id_register = 0xE0042000;
break;
case CORTEX_M23_PARTNO: /* GD32E23x devices */
device_id_register = 0x40015800;
break;
default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
@ -674,6 +677,9 @@ static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_i
case CORTEX_M4_PARTNO: /* STM32F3x devices */
flash_size_reg = 0x1FFFF7CC;
break;
case CORTEX_M23_PARTNO: /* GD32E23x devices */
flash_size_reg = 0x1FFFF7E0;
break;
default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
@ -756,8 +762,8 @@ static int stm32x_probe(struct flash_bank *bank)
page_size = 1024;
stm32x_info->ppage_size = 4;
max_flash_size_in_kb = 128;
/* GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID
with STM32F101/2/3 medium-density line,
/* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
share DEV_ID with STM32F101/2/3 medium-density line,
however they use a REV_ID different from any STM32 device.
The main difference is another offset of user option bits
(like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
@ -774,6 +780,11 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->user_data_offset = 16;
stm32x_info->option_offset = 6;
break;
case 0x1909: /* gd32e23x */
stm32x_info->user_data_offset = 16;
stm32x_info->option_offset = 6;
max_flash_size_in_kb = 64;
break;
}
break;
case 0x412: /* stm32f1x low-density */
@ -984,6 +995,10 @@ static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *c
device_str = "GD32F3x0";
break;
case 0x1909: /* gd32e23x */
device_str = "GD32E23x";
break;
case 0x2000:
rev_str = "B";
break;

3
src/flash/startup.tcl
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@ -121,3 +121,6 @@ proc stm32l5x args { eval stm32l4x $args }
proc stm32u5x args { eval stm32l4x $args }
proc stm32wbx args { eval stm32l4x $args }
proc stm32wlx args { eval stm32l4x $args }
# gd32e23x uses the same flash driver as the stm32f1x
proc gd32e23x args { eval stm32f1x $args }

74
tcl/target/gd32e23x.cfg Normal file
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@ -0,0 +1,74 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# script for GigaDevice gd32e23x Cortex-M23 Series
# https://www.gigadevice.com/microcontroller/gd32e230c8t6/
#
# gd32e23x devices support SWD transports only.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME gd32e23x
}
# Work-area is a space in RAM used for flash programming
# By default use 4kB (as found on some GD32E230s)
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1000
}
# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
set _FLASH_SIZE $FLASH_SIZE
} else {
# autodetect size
set _FLASH_SIZE 0
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# this is the SW-DP tap id not the jtag tap id
set _CPUTAPID 0x0bf11477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
# SWD speed (may be updated to higher value in board config file)
adapter speed 1000
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event examine-end {
# Debug clock enable
# RCU_APB2EN |= DBGMCUEN
mmw 0x40021018 0x00400000 0
# Stop watchdog counters during halt
# DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
mmw 0x40015804 0x00000307 0
}