native line endings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2603 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
0a7158140a
commit
5c50cf802c
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@ -1,55 +1,55 @@
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#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config srst_only srst_pulls_trst
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91sam7s
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x3f0f0f0f
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
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$_TARGETNAME configure -event reset-init {
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soft_reset_halt
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# RSTC_CR : Reset peripherals
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mww 0xfffffd00 0xa5000004
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# disable watchdog
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mww 0xfffffd44 0x00008000
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# enable user reset
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mww 0xfffffd08 0xa5000001
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# CKGR_MOR : enable the main oscillator
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mww 0xfffffc20 0x00000601
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sleep 10
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# CKGR_PLLR: 96.1097 MHz
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mww 0xfffffc2c 0x00481c0e
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sleep 10
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# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
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mww 0xfffffc30 0x00000007
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sleep 10
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# MC_FMR: flash mode (FWS=1,FMCN=73)
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mww 0xffffff60 0x00490100
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sleep 100
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}
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
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#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
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flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
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# For more information about the configuration files, take a look at:
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# openocd.texi
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#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config srst_only srst_pulls_trst
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91sam7s
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x3f0f0f0f
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
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$_TARGETNAME configure -event reset-init {
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soft_reset_halt
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# RSTC_CR : Reset peripherals
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mww 0xfffffd00 0xa5000004
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# disable watchdog
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mww 0xfffffd44 0x00008000
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# enable user reset
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mww 0xfffffd08 0xa5000001
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# CKGR_MOR : enable the main oscillator
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mww 0xfffffc20 0x00000601
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sleep 10
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# CKGR_PLLR: 96.1097 MHz
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mww 0xfffffc2c 0x00481c0e
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sleep 10
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# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
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mww 0xfffffc30 0x00000007
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sleep 10
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# MC_FMR: flash mode (FWS=1,FMCN=73)
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mww 0xffffff60 0x00490100
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sleep 100
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}
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
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#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
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flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
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# For more information about the configuration files, take a look at:
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# openocd.texi
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@ -1,44 +1,44 @@
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######################################
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# Target: Atmel AT91SAM9260
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######################################
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91sam9260
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x0792603f
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}
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reset_config trst_and_srst separate trst_push_pull srst_open_drain
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#
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag_nsrst_delay 300
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jtag_ntrst_delay 10
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jtag_rclk 3
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######################
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# Target configuration
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######################
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
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# Internal sram1 memory
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
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######################################
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# Target: Atmel AT91SAM9260
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######################################
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91sam9260
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x0792603f
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}
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reset_config trst_and_srst separate trst_push_pull srst_open_drain
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#
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag_nsrst_delay 300
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jtag_ntrst_delay 10
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jtag_rclk 3
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######################
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# Target configuration
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######################
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
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# Internal sram1 memory
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
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@ -1,8 +1,8 @@
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# Atmel AT91SAM7S-EK
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# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
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set CHIPNAME at91sam7s256
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source [find target/at91sam7sx.cfg]
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# Atmel AT91SAM7S-EK
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# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
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set CHIPNAME at91sam7s256
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source [find target/at91sam7sx.cfg]
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@ -1,81 +1,81 @@
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################################################################################
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# Atmel AT91SAM9260-EK eval board
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#
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# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
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#
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# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
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# OSCSEL configured for external 32.768 kHz crystal
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#
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# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
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#
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################################################################################
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# We add to the minimal configuration.
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source [find target/at91sam9260.cfg]
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# By default S1 is open and this means that NTRST is not connected.
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# The reset_config in target/at91sam9260.cfg is overridden here.
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# (or S1 must be populated with a 0 Ohm resistor)
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reset_config srst_only
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$_TARGETNAME configure -event reset-start {
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# At reset CPU runs at 32.768 kHz.
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# JTAG Frequency must be 6 times slower if RCLK is not supported.
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jtag_rclk 5
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halt
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
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arm926ejs mww_phys 0xfffffd08 0xa5000501
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}
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$_TARGETNAME configure -event reset-init {
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mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
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sleep 10 # wait 10 ms
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mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
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sleep 10 # wait 10 ms
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mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
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sleep 10 # wait 10 ms
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# Increase JTAG Speed to 6 MHz if RCLK is not supported
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jtag_rclk 6000
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
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mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
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mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
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mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
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mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
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}
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################################################################################
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# Atmel AT91SAM9260-EK eval board
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#
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# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
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#
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# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
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# OSCSEL configured for external 32.768 kHz crystal
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#
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# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
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#
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################################################################################
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# We add to the minimal configuration.
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source [find target/at91sam9260.cfg]
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# By default S1 is open and this means that NTRST is not connected.
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# The reset_config in target/at91sam9260.cfg is overridden here.
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# (or S1 must be populated with a 0 Ohm resistor)
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reset_config srst_only
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$_TARGETNAME configure -event reset-start {
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# At reset CPU runs at 32.768 kHz.
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# JTAG Frequency must be 6 times slower if RCLK is not supported.
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jtag_rclk 5
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halt
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
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arm926ejs mww_phys 0xfffffd08 0xa5000501
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}
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$_TARGETNAME configure -event reset-init {
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mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
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sleep 10 # wait 10 ms
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mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
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sleep 10 # wait 10 ms
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mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
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sleep 10 # wait 10 ms
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# Increase JTAG Speed to 6 MHz if RCLK is not supported
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jtag_rclk 6000
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
|
||||
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||||
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
|
||||
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
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||||
|
||||
mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
|
||||
|
||||
mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
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||||
mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
|
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mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
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}
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|
|
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@ -1,96 +1,96 @@
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# Thanks to Pieter Conradie for this script!
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||||
#
|
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# Unknown vendor board contains:
|
||||
#
|
||||
# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
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# OSCSEL configured for internal RC oscillator (22 to 42 kHz)
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#
|
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# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
|
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# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
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##################################################################
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|
||||
# We add to the minimal configuration.
|
||||
source [find target/at91sam9260.cfg]
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||||
|
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$_TARGETNAME configure -event reset-start {
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# At reset CPU runs at 22 to 42 kHz.
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# JTAG Frequency must be 6 times slower.
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jtag_rclk 3
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halt
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
|
||||
arm926ejs mww_phys 0xfffffd08 0xa5000501
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}
|
||||
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
|
||||
|
||||
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
|
||||
sleep 20 # wait 20 ms
|
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mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
|
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sleep 10 # wait 10 ms
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mww 0xfffffc28 0x205dbf09 # CKGR_PLLAR: Set PLLA Register for 192.512MHz
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sleep 20 # wait 20 ms
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||||
mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
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sleep 10 # wait 10 ms
|
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mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
|
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sleep 10 # wait 10 ms
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||||
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# Increase JTAG Speed to 6 MHz if RCLK is not supported
|
||||
jtag_rclk 6000
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||||
|
||||
arm7_9 dcc_downloads enable # Enable faster DCC downloads
|
||||
|
||||
mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
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mww 0xffffec04 0x09070806 # SMC_PULSE0
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mww 0xffffec08 0x000d000b # SMC_CYCLE0
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mww 0xffffec0c 0x00001003 # SMC_MODE0
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flash probe 0 # Identify flash bank 0
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|
||||
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
|
||||
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
|
||||
mww 0xfffff860 0xffff0000 # PIO_PUDR : Disable D15..D31 pull-ups
|
||||
|
||||
mww 0xffffef1c 0x00010102 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
|
||||
# VDDIOMSEL set for +3V3 memory
|
||||
# Disable D0..D15 pull-ups
|
||||
|
||||
mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
|
||||
|
||||
mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea04 0x2a2 # SDRAMC_TR : Set refresh timer count to 7us
|
||||
}
|
||||
|
||||
|
||||
#####################
|
||||
# Flash configuration
|
||||
#####################
|
||||
|
||||
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
|
||||
flash bank cfi 0x10000000 0x01000000 2 2 0
|
||||
|
||||
|
||||
# Thanks to Pieter Conradie for this script!
|
||||
#
|
||||
# Unknown vendor board contains:
|
||||
#
|
||||
# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
|
||||
# OSCSEL configured for internal RC oscillator (22 to 42 kHz)
|
||||
#
|
||||
# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
|
||||
# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
|
||||
##################################################################
|
||||
|
||||
# We add to the minimal configuration.
|
||||
source [find target/at91sam9260.cfg]
|
||||
|
||||
$_TARGETNAME configure -event reset-start {
|
||||
# At reset CPU runs at 22 to 42 kHz.
|
||||
# JTAG Frequency must be 6 times slower.
|
||||
jtag_rclk 3
|
||||
halt
|
||||
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
|
||||
arm926ejs mww_phys 0xfffffd08 0xa5000501
|
||||
}
|
||||
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
|
||||
|
||||
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
|
||||
sleep 20 # wait 20 ms
|
||||
mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
|
||||
sleep 10 # wait 10 ms
|
||||
mww 0xfffffc28 0x205dbf09 # CKGR_PLLAR: Set PLLA Register for 192.512MHz
|
||||
sleep 20 # wait 20 ms
|
||||
mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
|
||||
sleep 10 # wait 10 ms
|
||||
mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
|
||||
sleep 10 # wait 10 ms
|
||||
|
||||
# Increase JTAG Speed to 6 MHz if RCLK is not supported
|
||||
jtag_rclk 6000
|
||||
|
||||
arm7_9 dcc_downloads enable # Enable faster DCC downloads
|
||||
|
||||
mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
|
||||
mww 0xffffec04 0x09070806 # SMC_PULSE0
|
||||
mww 0xffffec08 0x000d000b # SMC_CYCLE0
|
||||
mww 0xffffec0c 0x00001003 # SMC_MODE0
|
||||
|
||||
flash probe 0 # Identify flash bank 0
|
||||
|
||||
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
|
||||
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
|
||||
mww 0xfffff860 0xffff0000 # PIO_PUDR : Disable D15..D31 pull-ups
|
||||
|
||||
mww 0xffffef1c 0x00010102 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
|
||||
# VDDIOMSEL set for +3V3 memory
|
||||
# Disable D0..D15 pull-ups
|
||||
|
||||
mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
|
||||
|
||||
mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea04 0x2a2 # SDRAMC_TR : Set refresh timer count to 7us
|
||||
}
|
||||
|
||||
|
||||
#####################
|
||||
# Flash configuration
|
||||
#####################
|
||||
|
||||
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
|
||||
flash bank cfi 0x10000000 0x01000000 2 2 0
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue