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remove TAP_INVALID as argument to jtag_add_xxx() fn's

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git-svn-id: svn://svn.berlios.de/openocd/trunk@2042 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2009-06-04 11:33:36 +00:00
parent bb1a1ddb54
commit 6468859389
18 changed files with 71 additions and 71 deletions
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10
src/flash/str9xpec.c
View File

@ -539,7 +539,7 @@ static int str9xpec_lock_device(struct flash_bank_s *bank)
field.out_value = NULL;
field.in_value = &status;
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
jtag_execute_queue();
} while(!(status & ISC_STATUS_BUSY));
@ -620,7 +620,7 @@ static int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
field.out_value = &sector;
field.in_value = NULL;
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
return ERROR_OK;
}
@ -717,7 +717,7 @@ static int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32
field.out_value = NULL;
field.in_value = scanbuf;
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
jtag_execute_queue();
status = buf_get_u32(scanbuf, 0, 8);
@ -767,7 +767,7 @@ static int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32
field.out_value = NULL;
field.in_value = scanbuf;
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
jtag_execute_queue();
status = buf_get_u32(scanbuf, 0, 8);
@ -959,7 +959,7 @@ static int str9xpec_write_options(struct flash_bank_s *bank)
field.out_value = NULL;
field.in_value = &status;
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
jtag_execute_queue();
} while(!(status & ISC_STATUS_BUSY));

2
src/jtag/jtag.c
View File

@ -2228,7 +2228,7 @@ static int handle_runtest_command(struct command_context_s *cmd_ctx, char *cmd,
return ERROR_COMMAND_SYNTAX_ERROR;
}
jtag_add_runtest(strtol(args[0], NULL, 0), TAP_INVALID);
jtag_add_runtest(strtol(args[0], NULL, 0), jtag_add_end_state(TAP_INVALID));
jtag_execute_queue();
return ERROR_OK;

2
src/target/arm11.h
View File

@ -47,7 +47,7 @@
23 * ARM11_REGCACHE_MODEREGS + \
9 * ARM11_REGCACHE_FREGS)
#define ARM11_TAP_DEFAULT TAP_INVALID
#define ARM11_TAP_DEFAULT jtag_add_end_state(TAP_INVALID)
#define CHECK_RETVAL(action) \

6
src/target/arm720t.c
View File

@ -119,15 +119,15 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
if (in)
{
fields[1].in_value = (u8 *)in;
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm7flip32, (u8 *)in);
} else
{
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
}
if (clock)
jtag_add_runtest(0, TAP_INVALID);
jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
if((retval = jtag_execute_queue()) != ERROR_OK)

12
src/target/arm7tdmi.c
View File

@ -147,9 +147,9 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int
2,
arm7tdmi_num_bits,
values,
TAP_INVALID);
jtag_add_end_state(TAP_INVALID));
jtag_add_runtest(0, TAP_INVALID);
jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID));
return ERROR_OK;
}
@ -187,11 +187,11 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[1].out_value = NULL;
fields[1].in_value = (u8 *)in;
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm7flip32, (u8 *)in);
jtag_add_runtest(0, TAP_INVALID);
jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
@ -277,11 +277,11 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[1].out_value = NULL;
jtag_alloc_in_value32(&fields[1]);
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback4(arm7endianness, in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
jtag_add_runtest(0, TAP_INVALID);
jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{

8
src/target/arm920t.c
View File

@ -127,11 +127,11 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
fields[1].in_value = (u8 *)value;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
@ -180,7 +180,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
@ -227,7 +227,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);

8
src/target/arm926ejs.c
View File

@ -157,7 +157,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
/*TODO: add timeout*/
do
@ -165,7 +165,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
@ -227,14 +227,14 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
/*TODO: add timeout*/
do
{
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, TAP_INVALID);
jtag_add_dr_scan(4, fields, jtag_add_end_state(TAP_INVALID));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;

6
src/target/arm966e.c
View File

@ -189,11 +189,11 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
fields[2].out_value = &nr_w_buf;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
fields[1].in_value = (u8 *)value;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
@ -244,7 +244,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
fields[2].out_value = &nr_w_buf;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);

14
src/target/arm9tdmi.c
View File

@ -204,16 +204,16 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
if (in)
{
fields[0].in_value=(u8 *)in;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm_le_to_h_u32, (u8 *)in);
}
else
{
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
}
jtag_add_runtest(0, TAP_INVALID);
jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
@ -263,11 +263,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[2].out_value = NULL;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm_le_to_h_u32, (u8 *)in);
jtag_add_runtest(0, TAP_INVALID);
jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
@ -330,11 +330,11 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[2].out_value = NULL;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback4(arm9endianness, in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
jtag_add_runtest(0, TAP_INVALID);
jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID));
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{

6
src/target/arm_adi_v5.c
View File

@ -83,7 +83,7 @@ int adi_jtag_dp_scan(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *o
fields[1].out_value = outvalue;
fields[1].in_value = invalue;
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
return ERROR_OK;
}
@ -118,13 +118,13 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u
if (invalue)
{
fields[1].in_value = (u8 *)invalue;
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm_le_to_h_u32, (u8 *)invalue);
} else
{
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
}
return ERROR_OK;

6
src/target/arm_jtag.c
View File

@ -53,13 +53,13 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr, void *no_verify_ca
if (no_verify_capture==NULL)
{
jtag_add_ir_scan(1, &field, TAP_INVALID);
jtag_add_ir_scan(1, &field, jtag_add_end_state(TAP_INVALID));
} else
{
/* FIX!!!! this is a kludge!!! arm926ejs.c should reimplement this arm_jtag_set_instr to
* have special verification code.
*/
jtag_add_ir_scan_noverify(1, &field, TAP_INVALID);
jtag_add_ir_scan_noverify(1, &field, jtag_add_end_state(TAP_INVALID));
}
}
@ -86,7 +86,7 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
1,
num_bits,
values,
TAP_INVALID);
jtag_add_end_state(TAP_INVALID));
jtag_info->cur_scan_chain = new_scan_chain;
}

14
src/target/embeddedice.c
View File

@ -266,7 +266,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
fields[0].in_value = reg->value;
fields[0].check_value = check_value;
@ -278,7 +278,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
*/
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
jtag_add_dr_scan_check(3, fields, TAP_INVALID);
jtag_add_dr_scan_check(3, fields, jtag_add_end_state(TAP_INVALID));
return ERROR_OK;
}
@ -314,7 +314,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
while (size > 0)
{
@ -325,7 +325,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
fields[0].in_value = (u8 *)data;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(arm_le_to_h_u32, (u8 *)data);
data++;
@ -420,7 +420,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
while (size > 0)
{
buf_set_u32(fields[0].out_value, 0, 32, *data);
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
data++;
size--;
@ -471,11 +471,11 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
gettimeofday(&lap, NULL);
do
{
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;

2
src/target/embeddedice.h
View File

@ -121,7 +121,7 @@ static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_add
3,
embeddedice_num_bits,
values,
TAP_INVALID);
jtag_add_end_state(TAP_INVALID));
}
void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count);

12
src/target/etb.c
View File

@ -63,7 +63,7 @@ static int etb_set_instr(etb_t *etb, u32 new_instr)
field.in_value = NULL;
jtag_add_ir_scan(1, &field, TAP_INVALID);
jtag_add_ir_scan(1, &field, jtag_add_end_state(TAP_INVALID));
free(field.out_value);
}
@ -86,7 +86,7 @@ static int etb_scann(etb_t *etb, u32 new_scan_chain)
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
etb->cur_scan_chain = new_scan_chain;
@ -190,7 +190,7 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
for (i = 0; i < num_frames; i++)
{
@ -204,7 +204,7 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
buf_set_u32(fields[1].out_value, 0, 7, 0);
fields[0].in_value = (u8 *)(data+i);
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_add_callback(etb_getbuf, (u8 *)(data+i));
}
@ -252,7 +252,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
@ -262,7 +262,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[0].check_value = check_value;
fields[0].check_mask = check_mask;
jtag_add_dr_scan_check(3, fields, TAP_INVALID);
jtag_add_dr_scan_check(3, fields, jtag_add_end_state(TAP_INVALID));
free(fields[1].out_value);
free(fields[2].out_value);

6
src/target/etm.c
View File

@ -347,13 +347,13 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
fields[0].in_value = reg->value;
fields[0].check_value = check_value;
fields[0].check_mask = check_mask;
jtag_add_dr_scan_check(3, fields, TAP_INVALID);
jtag_add_dr_scan_check(3, fields, jtag_add_end_state(TAP_INVALID));
free(fields[1].out_value);
free(fields[2].out_value);
@ -430,7 +430,7 @@ int etm_write_reg(reg_t *reg, u32 value)
buf_set_u32(fields[2].out_value, 0, 1, 1);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
return ERROR_OK;
}

4
src/target/feroceon.c
View File

@ -159,9 +159,9 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
/* no jtag_add_runtest(0, TAP_INVALID) here */
/* no jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID)) here */
return ERROR_OK;
}

8
src/target/mips_ejtag.c
View File

@ -50,7 +50,7 @@ int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, void *delete_m
jtag_add_ir_scan(1, &field, TAP_INVALID);
jtag_add_ir_scan(1, &field, jtag_add_end_state(TAP_INVALID));
}
return ERROR_OK;
@ -73,7 +73,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode)
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
if (jtag_execute_queue() != ERROR_OK)
{
@ -100,7 +100,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode)
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
if (jtag_execute_queue() != ERROR_OK)
{
@ -131,7 +131,7 @@ int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data)
jtag_add_dr_scan(1, &field, TAP_INVALID);
jtag_add_dr_scan(1, &field, jtag_add_end_state(TAP_INVALID));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{

16
src/target/xscale.c
View File

@ -212,7 +212,7 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr)
u8 tmp[4];
field.in_value = tmp;
jtag_add_ir_scan(1, &field, TAP_INVALID);
jtag_add_ir_scan(1, &field, jtag_add_end_state(TAP_INVALID));
/* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
jtag_check_value_mask(&field, tap->expected, tap->expected_mask);
@ -262,7 +262,7 @@ int xscale_read_dcsr(target_t *target)
u8 tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
@ -285,7 +285,7 @@ int xscale_read_dcsr(target_t *target)
jtag_add_end_state(TAP_IDLE);
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
@ -347,7 +347,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
jtag_add_runtest(1, TAP_INVALID); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
jtag_add_runtest(1, jtag_add_end_state(TAP_INVALID)); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
int attempts=0;
@ -725,7 +725,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
u8 tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(3, fields, TAP_INVALID);
jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask);
@ -800,7 +800,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
fields[0].num_bits = 32;
fields[0].out_value = packet;
@ -816,7 +816,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
memcpy(&value, packet, sizeof(u32));
cmd = parity(value);
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
}
jtag_execute_queue();
@ -862,7 +862,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
jtag_add_dr_scan(2, fields, TAP_INVALID);
jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_INVALID));
return ERROR_OK;
}