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tcl/target/stm32f3: fix reset init for stlink 

Use mmw to manipulate only selected bits of the word. msb and mwb verify the
memory location and may error on PLLRDY set as a result of PLLON written.

Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d
Reported-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2702
Tested-by: jenkins
This commit is contained in:
Paul Fertser 2015-04-09 15:20:22 +03:00
parent e7e1396578
commit 68921d2316
1 changed files with 5 additions and 5 deletions
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10
tcl/target/stm32f3x.cfg
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@ -104,11 +104,11 @@ proc stm32f3x_default_examine_end {} {
proc stm32f3x_default_reset_init {} {
# Configure PLL to boost clock to HSI x 8 (64 MHz)
mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
mwh 0x40021002 0x0100 ;# RCC_CR[31:16] = PLLON
mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
sleep 10 ;# Wait for PLL to lock
mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1]
mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
sleep 10 ;# Wait for PLL to lock
mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
# Boost JTAG frequency
adapter_khz 8000