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target: create/use register_cache_invalidate() 

Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:

 - armv4_5_invalidate_core_regs()
 - armv7m_invalidate_core_regs
 - mips32_invalidate_core_regs() too.

Make cache->num_regs be unsigned, avoiding various errors.

Net code shrink and simplification.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-11-19 19:02:10 -08:00
parent 31fb7788a6
commit 71cde5e359
14 changed files with 47 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/target/arm7_9_common.c
View File

@ -1040,7 +1040,7 @@ int arm7_9_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
{
@ -1224,10 +1224,7 @@ int arm7_9_soft_reset_halt(struct target *target)
}
/* all register content is now invalid */
if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
{
return retval;
}
register_cache_invalidate(armv4_5->core_cache);
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
@ -1921,7 +1918,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
if (!debug_execution)
{
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(armv4_5->core_cache);
target->state = TARGET_RUNNING;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
@ -2064,7 +2061,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
arm7_9->disable_single_step(target);
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(armv4_5->core_cache);
if (err != ERROR_OK)
{

16
src/target/armv4_5.c
View File

@ -436,22 +436,6 @@ static const struct reg_arch_type arm_reg_type = {
.set = armv4_5_set_core_reg,
};
/** Marks the contents of the register cache as invalid (and clean). */
int armv4_5_invalidate_core_regs(struct target *target)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list;
for (unsigned i = 0; i < num_regs; i++, reg++) {
reg->valid = 0;
reg->dirty = 0;
}
/* FIXME don't bother returning a value then */
return ERROR_OK;
}
struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
{
int num_regs = ARRAY_SIZE(arm_core_regs);

2
src/target/armv4_5.h
View File

@ -162,8 +162,6 @@ int armv4_5_run_algorithm(struct target *target,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);
int armv4_5_invalidate_core_regs(struct target *target);
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,

15
src/target/armv7m.c
View File

@ -246,21 +246,6 @@ static int armv7m_write_core_reg(struct target *target, unsigned num)
return ERROR_OK;
}
/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
int armv7m_invalidate_core_regs(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
for (i = 0; i < armv7m->core_cache->num_regs; i++)
{
armv7m->core_cache->reg_list[i].valid = 0;
armv7m->core_cache->reg_list[i].dirty = 0;
}
return ERROR_OK;
}
/**
* Returns generic ARM userspace registers to GDB.
* GDB doesn't quite understand that most ARMs don't have floating point

5
src/target/cortex_a8.c
View File

@ -545,7 +545,7 @@ static int cortex_a8_resume(struct target *target, int current,
target->state = TARGET_RUNNING;
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(armv4_5->core_cache);
if (!debug_execution)
{
@ -1182,11 +1182,12 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
static int cortex_a8_assert_reset(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
LOG_DEBUG(" ");
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(armv7a->armv4_5_common.core_cache);
target->state = TARGET_RESET;

11
src/target/cortex_m3.c
View File

@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
}
swjdp_transaction_endcheck(swjdp);
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
/* make sure we have latest dhcsr flags */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@ -510,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
target->state = TARGET_RESET;
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
while (timeout < 100)
{
@ -617,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
register_cache_invalidate(armv7m->core_cache);
if (!debug_execution)
{
target->state = TARGET_RUNNING;
@ -673,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
@ -812,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (target->reset_halt)
{

2
src/target/etm.c
View File

@ -234,7 +234,7 @@ static const struct reg_arch_type etm_scan6_type = {
static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
{
struct reg_cache *cache = etm_ctx->reg_cache;
int i;
unsigned i;
for (i = 0; i < cache->num_regs; i++) {
struct etm_reg *reg = cache->reg_list[i].arch_info;

15
src/target/mips32.c
View File

@ -175,21 +175,6 @@ int mips32_write_core_reg(struct target *target, int num)
return ERROR_OK;
}
int mips32_invalidate_core_regs(struct target *target)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target->arch_info;
int i;
for (i = 0; i < mips32->core_cache->num_regs; i++)
{
mips32->core_cache->reg_list[i].valid = 0;
mips32->core_cache->reg_list[i].dirty = 0;
}
return ERROR_OK;
}
int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
/* get pointers to arch-specific information */

1
src/target/mips32.h
View File

@ -147,7 +147,6 @@ int mips32_examine(struct target *target);
int mips32_register_commands(struct command_context *cmd_ctx);
int mips32_invalidate_core_regs(struct target *target);
int mips32_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size);

6
src/target/mips_m4k.c
View File

@ -309,7 +309,7 @@ int mips_m4k_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
mips32_invalidate_core_regs(target);
register_cache_invalidate(mips32->core_cache);
if (target->reset_halt)
{
@ -410,7 +410,7 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
mips32_invalidate_core_regs(target);
register_cache_invalidate(mips32->core_cache);
if (!debug_execution)
{
@ -467,7 +467,7 @@ int mips_m4k_step(struct target *target, int current, uint32_t address, int hand
mips_ejtag_exit_debug(ejtag_info);
/* registers are now invalid */
mips32_invalidate_core_regs(target);
register_cache_invalidate(mips32->core_cache);
if (breakpoint)
mips_m4k_set_breakpoint(target, breakpoint);

22
src/target/register.c
View File

@ -28,11 +28,20 @@
#include "register.h"
#include "log.h"
/**
* @file
* Holds utilities to work with register caches.
*
* OpenOCD uses machine registers internally, and exposes them by name
* to Tcl scripts. Sets of related registers are grouped into caches.
* For example, a CPU core will expose a set of registers, and there
* may be separate registers associated with debug or trace modules.
*/
struct reg* register_get_by_name(struct reg_cache *first,
const char *name, bool search_all)
{
int i;
unsigned i;
struct reg_cache *cache = first;
while (cache)
@ -65,6 +74,17 @@ struct reg_cache** register_get_last_cache_p(struct reg_cache **first)
return cache_p;
}
/** Marks the contents of the register cache as invalid (and clean). */
void register_cache_invalidate(struct reg_cache *cache)
{
struct reg *reg = cache->reg_list;
for (unsigned n = cache->num_regs; n != 0; n--, reg++) {
reg->valid = 0;
reg->dirty = 0;
}
}
static int register_get_dummy_core_reg(struct reg *reg)
{
return ERROR_OK;

3
src/target/register.h
View File

@ -41,7 +41,7 @@ struct reg_cache
char *name;
struct reg_cache *next;
struct reg *reg_list;
int num_regs;
unsigned num_regs;
};
struct reg_arch_type
@ -53,6 +53,7 @@ struct reg_arch_type
struct reg* register_get_by_name(struct reg_cache *first,
const char *name, bool search_all);
struct reg_cache** register_get_last_cache_p(struct reg_cache **first);
void register_cache_invalidate(struct reg_cache *cache);
void register_init_dummy(struct reg *reg);

8
src/target/target.c
View File

@ -1860,7 +1860,7 @@ COMMAND_HANDLER(handle_reg_command)
{
struct target *target;
struct reg *reg = NULL;
int count = 0;
unsigned count = 0;
char *value;
LOG_DEBUG("-");
@ -1875,7 +1875,7 @@ COMMAND_HANDLER(handle_reg_command)
count = 0;
while (cache)
{
int i;
unsigned i;
command_print(CMD_CTX, "===== %s", cache->name);
@ -1917,10 +1917,10 @@ COMMAND_HANDLER(handle_reg_command)
count = 0;
while (cache)
{
int i;
unsigned i;
for (i = 0; i < cache->num_regs; i++)
{
if (count++ == (int)num)
if (count++ == num)
{
reg = &cache->reg_list[i];
break;

7
src/target/xscale.c
View File

@ -1322,7 +1322,7 @@ static int xscale_resume(struct target *target, int current,
if (!debug_execution)
{
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(armv4_5->core_cache);
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
}
@ -1401,8 +1401,7 @@ static int xscale_step_inner(struct target *target, int current,
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
return retval;
register_cache_invalidate(armv4_5->core_cache);
/* wait for and process debug entry */
if ((retval = xscale_debug_entry(target)) != ERROR_OK)
@ -1538,7 +1537,7 @@ static int xscale_deassert_reset(struct target *target)
breakpoint = breakpoint->next;
}
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(xscale->armv4_5_common.core_cache);
/* FIXME mark hardware watchpoints got unset too. Also,
* at least some of the XScale registers are invalid...