Dirk Behme <dirk.behme@googlemail.com> Add minimalist Cortex A8 file
git-svn-id: svn://svn.berlios.de/openocd/trunk@1602 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
03fdabaaac
commit
7a93100c2d
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@ -14,12 +14,12 @@ METASOURCES = AUTO
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noinst_LIBRARIES = libtarget.a
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libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
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arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
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arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c arm_adi_v5.c \
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arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_a8.c arm_adi_v5.c \
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etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
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mips32_pracc.c mips32_dmaacc.c mips_ejtag.c avrt.c
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noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
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arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
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arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h arm_adi_v5.h \
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arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_a8.h arm_adi_v5.h \
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etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h avrt.h
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nobase_dist_pkglib_DATA =
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@ -0,0 +1,273 @@
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2009 by Dirk Behme *
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* dirk.behme@gmail.com - copy from cortex_m3 *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* Cortex-A8(tm) TRM, ARM DDI 0344H *
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* *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "replacements.h"
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#include "cortex_a8.h"
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#include "armv7m.h"
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#include "register.h"
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#include "target.h"
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#include "target_request.h"
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#include "log.h"
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#include "jtag.h"
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#include "arm_jtag.h"
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#include <stdlib.h>
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#include <string.h>
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/* cli handling */
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int cortex_a8_register_commands(struct command_context_s *cmd_ctx);
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/* forward declarations */
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int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp);
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target_type_t cortexa8_target =
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{
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.name = "cortex_a8",
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.poll = NULL,
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.arch_state = armv7m_arch_state,
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.target_request_data = NULL,
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.halt = NULL,
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.resume = NULL,
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.step = NULL,
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.assert_reset = NULL,
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.deassert_reset = NULL,
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.soft_reset_halt = NULL,
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.get_gdb_reg_list = armv7m_get_gdb_reg_list,
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.read_memory = cortex_a8_read_memory,
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.write_memory = cortex_a8_write_memory,
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.bulk_write_memory = NULL,
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.checksum_memory = NULL,
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.blank_check_memory = NULL,
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.run_algorithm = armv7m_run_algorithm,
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.add_breakpoint = NULL,
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.remove_breakpoint = NULL,
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.add_watchpoint = NULL,
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.remove_watchpoint = NULL,
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.register_commands = cortex_a8_register_commands,
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.target_create = cortex_a8_target_create,
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.init_target = NULL,
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.examine = NULL,
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.quit = NULL
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};
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int cortex_a8_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
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{
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u16 dcrdr;
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mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
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*ctrl = (u8)dcrdr;
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*value = (u8)(dcrdr >> 8);
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LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
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/* write ack back to software dcc register
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* signify we have read data */
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if (dcrdr & (1 << 0))
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{
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dcrdr = 0;
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mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
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}
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return ERROR_OK;
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}
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int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
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{
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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int retval;
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/* sanitize arguments */
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if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
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return ERROR_INVALID_ARGUMENTS;
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/* cortex_a8 handles unaligned memory access */
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switch (size)
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{
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case 4:
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retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
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break;
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default:
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LOG_ERROR("BUG: we shouldn't get here");
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exit(-1);
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}
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return retval;
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}
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int cortex_a8_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
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{
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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int retval;
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/* sanitize arguments */
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if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
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return ERROR_INVALID_ARGUMENTS;
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switch (size)
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{
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case 4:
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retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
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break;
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default:
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LOG_ERROR("BUG: we shouldn't get here");
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exit(-1);
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}
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return retval;
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}
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int cortex_a8_handle_target_request(void *priv)
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{
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target_t *target = priv;
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if (!target->type->examined)
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return ERROR_OK;
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armv7m_common_t *armv7m = target->arch_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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if (!target->dbg_msg_enabled)
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return ERROR_OK;
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if (target->state == TARGET_RUNNING)
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{
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u8 data;
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u8 ctrl;
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cortex_a8_dcc_read(swjdp, &data, &ctrl);
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/* check if we have data */
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if (ctrl & (1 << 0))
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{
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u32 request;
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/* we assume target is quick enough */
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request = data;
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cortex_a8_dcc_read(swjdp, &data, &ctrl);
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request |= (data << 8);
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cortex_a8_dcc_read(swjdp, &data, &ctrl);
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request |= (data << 16);
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cortex_a8_dcc_read(swjdp, &data, &ctrl);
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request |= (data << 24);
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target_request(target, request);
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}
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}
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return ERROR_OK;
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}
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int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap)
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{
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armv7m_common_t *armv7m;
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armv7m = &cortex_a8->armv7m;
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/* prepare JTAG information for the new target */
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cortex_a8->jtag_info.tap = tap;
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cortex_a8->jtag_info.scann_size = 4;
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armv7m->swjdp_info.dp_select_value = -1;
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armv7m->swjdp_info.ap_csw_value = -1;
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armv7m->swjdp_info.ap_tar_value = -1;
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armv7m->swjdp_info.jtag_info = &cortex_a8->jtag_info;
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/* initialize arch-specific breakpoint handling */
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cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
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cortex_a8->arch_info = NULL;
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/* register arch-specific functions */
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armv7m->examine_debug_reason = NULL;
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armv7m->pre_debug_entry = NULL;
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armv7m->post_debug_entry = NULL;
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armv7m->pre_restore_context = NULL;
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armv7m->post_restore_context = NULL;
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armv7m_init_arch_info(target, armv7m);
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armv7m->arch_info = cortex_a8;
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armv7m->load_core_reg_u32 = NULL;
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armv7m->store_core_reg_u32 = NULL;
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target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
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return ERROR_OK;
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}
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int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
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{
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cortex_a8_common_t *cortex_a8 = calloc(1,sizeof(cortex_a8_common_t));
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cortex_a8_init_arch_info(target, cortex_a8, target->tap);
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return ERROR_OK;
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}
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int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
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{
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int retval;
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retval = armv7m_register_commands(cmd_ctx);
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register_command(cmd_ctx, NULL, "cortex_a8", NULL, COMMAND_ANY, "cortex_a8 specific commands");
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return retval;
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}
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@ -0,0 +1,99 @@
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2009 by Dirk Behme *
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* dirk.behme@gmail.com - copy from cortex_m3 *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef CORTEX_A8_H
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#define CORTEX_A8_H
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#include "register.h"
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#include "target.h"
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#include "armv7m.h"
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extern char* cortex_a8_state_strings[];
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#define CORTEX_A8_COMMON_MAGIC 0x411fc082
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#define CPUID 0x54011D00
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/* Debug Control Block */
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#define DCB_DHCSR 0x54011DF0
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#define DCB_DCRSR 0x54011DF4
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#define DCB_DCRDR 0x54011DF8
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#define DCB_DEMCR 0x54011DFC
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typedef struct cortex_a8_fp_comparator_s
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{
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int used;
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int type;
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u32 fpcr_value;
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u32 fpcr_address;
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} cortex_a8_fp_comparator_t;
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typedef struct cortex_a8_dwt_comparator_s
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{
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int used;
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u32 comp;
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u32 mask;
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u32 function;
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u32 dwt_comparator_address;
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} cortex_a8_dwt_comparator_t;
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typedef struct cortex_a8_common_s
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{
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int common_magic;
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arm_jtag_t jtag_info;
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/* Context information */
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u32 dcb_dhcsr;
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u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
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u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
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/* Flash Patch and Breakpoint (FPB) */
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int fp_num_lit;
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int fp_num_code;
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int fp_code_available;
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int fpb_enabled;
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int auto_bp_type;
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cortex_a8_fp_comparator_t *fp_comparator_list;
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/* Data Watchpoint and Trace (DWT) */
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int dwt_num_comp;
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int dwt_comp_available;
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cortex_a8_dwt_comparator_t *dwt_comparator_list;
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/* Interrupts */
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int intlinesnum;
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u32 *intsetenable;
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armv7m_common_t armv7m;
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void *arch_info;
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} cortex_a8_common_t;
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extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
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int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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int cortex_a8_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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#endif /* CORTEX_A8_H */
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@ -101,6 +101,7 @@ extern target_type_t arm926ejs_target;
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extern target_type_t feroceon_target;
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extern target_type_t xscale_target;
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extern target_type_t cortexm3_target;
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extern target_type_t cortexa8_target;
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extern target_type_t arm11_target;
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extern target_type_t mips_m4k_target;
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extern target_type_t avr_target;
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@ -116,6 +117,7 @@ target_type_t *target_types[] =
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&feroceon_target,
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&xscale_target,
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&cortexm3_target,
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&cortexa8_target,
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&arm11_target,
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&mips_m4k_target,
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&avr_target,
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