Documentation : Add missing commands for ARM-v7A & R

Change-Id: I520fed122385d4d666bf91b754b1ac196b51d471
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/2875
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
This commit is contained in:
Evan Hunter 2015-07-17 12:37:35 +01:00 committed by Freddie Chopin
parent fabbb880ec
commit 7ae5b45f75
1 changed files with 48 additions and 0 deletions

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@ -7568,6 +7568,54 @@ fix CSW_SPROT from register AP_REG_CSW on selected dap.
Defaulting to 0.
@end deffn
@deffn Command {dap ti_be_32_quirks} [@option{enable}]
Set/get quirks mode for TI TMS450/TMS570 processors
Disabled by default
@end deffn
@subsection ARMv7-A specific commands
@cindex Cortex-A
@deffn Command {cortex_a cache_info}
display information about target caches
@end deffn
@deffn Command {cortex_a dbginit}
Initialize core debug
Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
@end deffn
@deffn Command {cortex_a smp_off}
Disable SMP mode
@end deffn
@deffn Command {cortex_a smp_on}
Enable SMP mode
@end deffn
@deffn Command {cortex_a smp_gdb} [core_id]
Display/set the current core displayed in GDB
@end deffn
@deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
Selects whether interrupts will be processed when single stepping
@end deffn
@deffn Command {cache_config l2x} [base way]
configure l2x cache
@end deffn
@subsection ARMv7-R specific commands
@cindex Cortex-R
@deffn Command {cortex_r dbginit}
Initialize core debug
Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
@end deffn
@subsection ARMv7-M specific commands
@cindex tracing
@cindex SWO