Add a new JTAG "setup" event; use for better DaVinci ICEpick support.
The model is that this fires after scanchain verification, when it's safe to call "jtag tapenable $TAPNAME". So it will fire as part of non-error paths of "init" and "reset" command processing. However it will *NOT* trigger during "jtag_reset" processing, which skips all scan chain verification, or after verification errors. ALSO: - switch DaVinci chips to use this new mechanism - log TAP activation/deactivation, since their IDCODEs aren't verified - unify "enum jtag_event" scripted event notifications - remove duplicative JTAG_TAP_EVENT_POST_RESET git-svn-id: svn://svn.berlios.de/openocd/trunk@2800 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
dbrownell
parent
16a7ad5799
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7c7467b34f
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@ -2428,12 +2428,18 @@ The TAP events currently defined are:
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@itemize @bullet
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@item @b{post-reset}
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@* The TAP has just completed a JTAG reset.
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For the first such handler called, the tap is still
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in the JTAG @sc{reset} state.
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The tap may still be in the JTAG @sc{reset} state.
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Handlers for these events might perform initialization sequences
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such as issuing TCK cycles, TMS sequences to ensure
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exit from the ARM SWD mode, and more.
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Because the scan chain has not yet been verified, handlers for these events
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@emph{should not issue commands which scan the JTAG IR or DR registers}
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of any particular target.
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@b{NOTE:} As this is written (September 2009), nothing prevents such access.
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@item @b{setup}
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@* The scan chain has been reset and verified.
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This handler may enable TAPs as needed.
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@item @b{tap-disable}
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@* The TAP needs to be disabled. This handler should
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implement @command{jtag tapdisable}
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@ -2450,7 +2456,7 @@ contents to be accurate), you might:
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@example
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jtag configure CHIP.jrc -event post-reset @{
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echo "Reset done"
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echo "JTAG Reset done"
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... non-scan jtag operations to be done after reset
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@}
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@end example
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@ -2493,20 +2499,30 @@ does include a kind of JTAG router functionality.
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In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
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shown below, and is implemented using TAP event handlers.
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So for example, when defining a TAP for a CPU connected to
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a JTAG router, you should define TAP event handlers using
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a JTAG router, your @file{target.cfg} file
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should define TAP event handlers using
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code that looks something like this:
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@example
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jtag configure CHIP.cpu -event tap-enable @{
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echo "Enabling CPU TAP"
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... jtag operations using CHIP.jrc
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@}
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jtag configure CHIP.cpu -event tap-disable @{
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echo "Disabling CPU TAP"
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... jtag operations using CHIP.jrc
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@}
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@end example
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Then you might want that CPU's TAP enabled almost all the time:
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@example
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jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
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@end example
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Note how that particular setup event handler declaration
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uses quotes to evaluate @code{$CHIP} when the event is configured.
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Using brackets @{ @} would cause it to be evaluated later,
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at runtime, when it might have a different value.
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@deffn Command {jtag tapdisable} dotted.name
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If necessary, disables the tap
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by sending it a @option{tap-disable} event.
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@ -61,8 +61,8 @@ static int jtag_error = ERROR_OK;
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static const char *jtag_event_strings[] =
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{
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[JTAG_TRST_ASSERTED] = "TAP reset",
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[JTAG_TAP_EVENT_SETUP] = "TAP setup",
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[JTAG_TAP_EVENT_ENABLE] = "TAP enabled",
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[JTAG_TAP_EVENT_POST_RESET] = "TAP post reset",
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[JTAG_TAP_EVENT_DISABLE] = "TAP disabled",
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};
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@ -489,7 +489,7 @@ void jtag_add_tlr(void)
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/* NOTE: order here matches TRST path in jtag_add_reset() */
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jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
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jtag_notify_reset();
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jtag_notify_event(JTAG_TRST_ASSERTED);
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}
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void jtag_add_pathmove(int num_states, const tap_state_t *path)
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@ -704,7 +704,7 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
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* sequence must match jtag_add_tlr().
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*/
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jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
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jtag_notify_reset();
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jtag_notify_event(JTAG_TRST_ASSERTED);
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}
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}
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}
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@ -1232,6 +1232,7 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx)
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{
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jtag_tap_t *tap;
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int retval;
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bool issue_setup = true;
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LOG_DEBUG("Init JTAG chain");
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@ -1249,13 +1250,21 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx)
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if (jtag_examine_chain() != ERROR_OK)
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{
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LOG_ERROR("Trying to use configured scan chain anyway...");
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issue_setup = false;
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}
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if (jtag_validate_ircapture() != ERROR_OK)
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{
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LOG_WARNING("Errors during IR capture, continuing anyway...");
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issue_setup = false;
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}
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if (issue_setup)
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jtag_notify_event(JTAG_TAP_EVENT_SETUP);
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else
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LOG_WARNING("Bypassing JTAG setup events due to errors");
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return ERROR_OK;
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}
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@ -192,23 +192,32 @@ extern unsigned jtag_tap_count(void);
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/*
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* There are three cases when JTAG_TRST_ASSERTED callback is invoked. The
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* event is invoked *after* TRST is asserted(or queued rather). It is illegal
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* to communicate with the JTAG interface during the callback(as there is
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* currently a queue being built).
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* - TRST_ASSERTED triggers two sets of callbacks, after operations to
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* reset the scan chain -- via TMS+TCK signaling, or deasserting the
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* nTRST signal -- are queued:
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*
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* - TMS reset
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* - SRST pulls TRST
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* - TRST asserted
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* + Callbacks in C code fire first, patching internal state
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* + Then post-reset event scripts fire ... activating JTAG circuits
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* via TCK cycles, exiting SWD mode via TMS sequences, etc
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*
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* TAP activation/deactivation is currently implemented outside the core
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* using scripted code that understands the specific router type.
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* During those callbacks, scan chain contents have not been validated.
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* JTAG operations that address a specific TAP (primarily DR/IR scans)
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* must *not* be queued.
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*
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* - TAP_EVENT_SETUP is reported after TRST_ASSERTED, and after the scan
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* chain has been validated. JTAG operations including scans that
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* target specific TAPs may be performed.
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*
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* - TAP_EVENT_ENABLE and TAP_EVENT_DISABLE implement TAP activation and
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* deactivation outside the core using scripted code that understands
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* the specific JTAG router type. They might be triggered indirectly
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* from EVENT_SETUP operations.
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*/
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enum jtag_event {
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JTAG_TRST_ASSERTED,
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JTAG_TAP_EVENT_SETUP,
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JTAG_TAP_EVENT_ENABLE,
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JTAG_TAP_EVENT_DISABLE,
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JTAG_TAP_EVENT_POST_RESET,
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};
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struct jtag_tap_event_action_s
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@ -643,8 +652,8 @@ extern void jtag_execute_queue_noclear(void);
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/// @returns the number of times the scan queue has been flushed
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int jtag_get_flush_queue_count(void);
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/// Notify all TAP's about a TLR reset
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void jtag_notify_reset(void);
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/// Report Tcl event to all TAPs
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void jtag_notify_event(enum jtag_event);
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/* can be implemented by hw + sw */
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@ -41,7 +41,8 @@
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#endif
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static const Jim_Nvp nvp_jtag_tap_event[] = {
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{ .value = JTAG_TAP_EVENT_POST_RESET, .name = "post-reset" },
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{ .value = JTAG_TRST_ASSERTED, .name = "post-reset" },
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{ .value = JTAG_TAP_EVENT_SETUP, .name = "setup" },
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{ .value = JTAG_TAP_EVENT_ENABLE, .name = "tap-enable" },
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{ .value = JTAG_TAP_EVENT_DISABLE, .name = "tap-disable" },
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@ -373,7 +374,7 @@ static void jtag_tap_handle_event(jtag_tap_t *tap, enum jtag_event e)
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for (jteap = tap->event_action; jteap != NULL; jteap = jteap->next) {
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if (jteap->event == e) {
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LOG_DEBUG("JTAG tap: %s event: %d (%s) action: %s\n",
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LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s",
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tap->dotted_name,
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e,
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Jim_Nvp_value2name_simple(nvp_jtag_tap_event, e)->name,
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@ -384,10 +385,12 @@ static void jtag_tap_handle_event(jtag_tap_t *tap, enum jtag_event e)
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case JTAG_TAP_EVENT_ENABLE:
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case JTAG_TAP_EVENT_DISABLE:
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/* NOTE: we currently assume the handlers
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* can't fail. That presumes later code
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* will be verifying the scan chains ...
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* can't fail. Right here is where we should
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* really be verifying the scan chains ...
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*/
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tap->enabled = (e == JTAG_TAP_EVENT_ENABLE);
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LOG_INFO("JTAG tap: %s %s", tap->dotted_name,
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tap->enabled ? "enabled" : "disabled");
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break;
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default:
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break;
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@ -586,13 +589,12 @@ static int jim_jtag_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
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}
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void jtag_notify_reset(void)
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void jtag_notify_event(enum jtag_event event)
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{
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jtag_tap_t *tap;
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for (tap = jtag_all_taps(); tap; tap = tap->next_tap)
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{
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jtag_tap_handle_event(tap, JTAG_TAP_EVENT_POST_RESET);
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}
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jtag_tap_handle_event(tap, event);
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}
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@ -9,11 +9,11 @@ if { [info exists CHIPNAME] } {
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# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
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# after JTAG reset until ICEpick is used to route them in.
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#set EMU01 "-disable"
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set EMU01 "-disable"
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# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
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# needing any ICEpick interaction.
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set EMU01 "-enable"
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#set EMU01 "-enable"
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source [find target/icepick.cfg]
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@ -50,6 +50,9 @@ if { [info exists JRC_TAPID ] } {
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
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jtag configure $_CHIPNAME.jrc -event setup \
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"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
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################
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# various symbol definitions, to avoid hard-wiring addresses
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@ -7,16 +7,15 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME dm365
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}
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#
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# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
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# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
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#
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# Also note: when running without RTCK before the PLLs are set up, you
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# may need to slow the JTAG clock down quite a lot (under 2 MHz).
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#
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# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
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# after JTAG reset until ICEpick is used to route them in.
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set EMU01 "-disable"
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# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
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# needing any ICEpick interaction.
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#set EMU01 "-enable"
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source [find target/icepick.cfg]
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set EMU01 "-enable"
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#set EMU01 "-disable"
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# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
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if { [info exists ETB_TAPID ] } {
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@ -46,6 +45,9 @@ if { [info exists JRC_TAPID ] } {
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
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jtag configure $_CHIPNAME.jrc -event setup \
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"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
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################
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# various symbol definitions, to avoid hard-wiring addresses
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@ -7,17 +7,15 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME dm6446
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}
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#
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# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
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# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
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# Override by setting EMU01 to "-disable".
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#
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# Also note: when running without RTCK before the PLLs are set up, you
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# may need to slow the JTAG clock down quite a lot (under 2 MHz).
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#
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# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
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# after JTAG reset until ICEpick is used to route them in.
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set EMU01 "-disable"
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# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
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# needing any ICEpick interaction.
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#set EMU01 "-enable"
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source [find target/icepick.cfg]
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set EMU01 "-enable"
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#set EMU01 "-disable"
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# Subsidiary TAP: unknown ... must enable via ICEpick
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jtag newtap $_CHIPNAME unknown -irlen 8 -disable
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@ -57,6 +55,10 @@ if { [info exists JRC_TAPID ] } {
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
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jtag configure $_CHIPNAME.jrc -event setup \
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"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
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################
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# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
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# and the ETB memory (4K) are other options, while trace is unused.
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# Little-endian; use the OpenOCD default.
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