armv7m: remove gdb register hacks
Now that we support the target description format we do not need these hacks anymore, we can now tell gdb what registers we support. Change-Id: Ie774231d296420b35efcf708bc4435475c87ff5e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1617 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Spencer Oliver
Andreas Fritiofson
parent
d14058db0a
commit
80a94681de
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@ -69,19 +69,6 @@ const int armv7m_msp_reg_map[17] = {
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ARMV7M_xPSR,
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};
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#ifdef ARMV7_GDB_HACKS
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uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
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struct reg armv7m_gdb_dummy_cpsr_reg = {
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.name = "GDB dummy cpsr register",
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.value = armv7m_gdb_dummy_cpsr_value,
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.dirty = 0,
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.valid = 1,
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.size = 32,
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.arch_info = NULL,
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};
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#endif
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/*
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* These registers are not memory-mapped. The ARMv7-M profile includes
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* memory mapped registers too, such as for the NVIC (interrupt controller)
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@ -281,17 +268,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
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for (i = 16; i < 24; i++)
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(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
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(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
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#ifdef ARMV7_GDB_HACKS
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/* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
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(*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
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/* ARMV7M is always in thumb mode, try to make GDB understand this
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* if it does not support this arch */
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*((char *)armv7m->arm.pc->value) |= 1;
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#else
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(*reg_list)[25] = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
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#endif
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return ERROR_OK;
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}
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@ -552,10 +529,6 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
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struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
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int i;
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#ifdef ARMV7_GDB_HACKS
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register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
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#endif
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/* Build the process context cache */
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cache->name = "arm v7m registers";
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cache->next = NULL;
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@ -30,16 +30,6 @@
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#include "arm_adi_v5.h"
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#include "arm.h"
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/* define for enabling armv7 gdb workarounds */
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#if 1
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#define ARMV7_GDB_HACKS
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#endif
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#ifdef ARMV7_GDB_HACKS
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extern uint8_t armv7m_gdb_dummy_cpsr_value[];
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extern struct reg armv7m_gdb_dummy_cpsr_reg;
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#endif
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extern const int armv7m_psp_reg_map[];
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extern const int armv7m_msp_reg_map[];
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@ -433,17 +433,6 @@ static int cortex_m3_debug_entry(struct target *target)
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r = arm->cpsr;
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xPSR = buf_get_u32(r->value, 0, 32);
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#ifdef ARMV7_GDB_HACKS
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/* FIXME this breaks on scan chains with more than one Cortex-M3.
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* Instead, each CM3 should have its own dummy value...
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*/
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/* copy real xpsr reg for gdb, setting thumb bit */
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buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
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buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
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armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
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armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
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#endif
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/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
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if (xPSR & 0xf00) {
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r->dirty = r->valid;
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@ -1232,17 +1221,8 @@ int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoin
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{
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struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
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if (cortex_m3->auto_bp_type) {
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if (cortex_m3->auto_bp_type)
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breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
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#ifdef ARMV7_GDB_HACKS
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if (breakpoint->length != 2) {
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/* XXX Hack: Replace all breakpoints with length != 2 with
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* a hardware breakpoint. */
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breakpoint->type = BKPT_HARD;
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breakpoint->length = 2;
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}
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#endif
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}
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if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
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if (breakpoint->type == BKPT_HARD) {
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@ -1540,18 +1520,6 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct adiv5_dap *swjdp = armv7m->arm.dap;
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#ifdef ARMV7_GDB_HACKS
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/* If the LR register is being modified, make sure it will put us
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* in "thumb" mode, or an INVSTATE exception will occur. This is a
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* hack to deal with the fact that gdb will sometimes "forge"
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* return addresses, and doesn't set the LSB correctly (i.e., when
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* printing expressions containing function calls, it sets LR = 0.)
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* Valid exception return codes have bit 0 set too.
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*/
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if (num == ARMV7M_R14)
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value |= 0x01;
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#endif
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/* NOTE: we "know" here that the register identifiers used
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* in the v7m header match the Cortex-M3 Debug Core Register
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* Selector values for R0..R15, xPSR, MSP, and PSP.
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@ -157,18 +157,6 @@ static int adapter_store_core_reg_u32(struct target *target,
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LOG_DEBUG("%s", __func__);
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#ifdef ARMV7_GDB_HACKS
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/* If the LR register is being modified, make sure it will put us
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* in "thumb" mode, or an INVSTATE exception will occur. This is a
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* hack to deal with the fact that gdb will sometimes "forge"
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* return addresses, and doesn't set the LSB correctly (i.e., when
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* printing expressions containing function calls, it sets LR = 0.)
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* Valid exception return codes have bit 0 set too.
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*/
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if (num == ARMV7M_R14)
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value |= 0x01;
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#endif
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/* NOTE: we "know" here that the register identifiers used
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* in the v7m header match the Cortex-M3 Debug Core Register
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* Selector values for R0..R15, xPSR, MSP, and PSP.
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