ARM966: help/usage updates

Usage syntax messages have the same EBNF as the User's Guide;
there should be no angle brackets in either place.

Fix the User's Guide to say where the magic CP15 bits are defined;
and add comments in case someone provides mcr/mrc methods.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2010-01-07 16:39:32 -08:00
parent e7965cd3eb
commit 82c0fb5277
2 changed files with 15 additions and 1 deletions

View File

@ -6030,6 +6030,10 @@ and ARM9 commands.
@deffn Command {arm966e cp15} regnum [value]
Display cp15 register @var{regnum};
else if a @var{value} is provided, that value is written to that register.
The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
ARM966E-S TRM.
There is no current control over bits 31..30 from that table,
as required for BIST support.
@end deffn
@subsection XScale specific commands

View File

@ -68,6 +68,13 @@ static int arm966e_verify_pointer(struct command_context *cmd_ctx,
return ERROR_OK;
}
/*
* REVISIT: The "read_cp15" and "write_cp15" commands could hook up
* to eventual mrc() and mcr() routines ... the reg_addr values being
* constructed (for CP15 only) from Opcode_1, Opcode_2, and CRn values.
* See section 7.3 of the ARM966E-S TRM.
*/
static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *value)
{
int retval = ERROR_OK;
@ -86,6 +93,9 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
/* REVISIT: table 7-2 shows that bits 31-31 need to be
* specified for accessing BIST registers ...
*/
fields[0].out_value = NULL;
fields[0].in_value = NULL;
@ -227,7 +237,7 @@ static const struct command_registration arm966e_exec_command_handlers[] = {
.name = "cp15",
.handler = arm966e_handle_cp15_command,
.mode = COMMAND_EXEC,
.usage = "<opcode> [value]",
.usage = "regnum [value]",
.help = "display/modify cp15 register",
},
COMMAND_REGISTRATION_DONE