From 82e76262a13299f11d0a73418a8e76558761dccc Mon Sep 17 00:00:00 2001 From: Tomas Vanek Date: Thu, 26 May 2022 13:08:48 +0200 Subject: [PATCH] target/riscv: use struct riscv_info instead of typedef riscv_info_t Make the main RISC-V structure more compliant with OpenOCD coding style. Other typedefs remains as is. Change-Id: I5657ad28fea8108fd66ab27b2dfe1c868dc5805b Signed-off-by: Tomas Vanek Reviewed-on: https://review.openocd.org/c/openocd/+/6998 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tim Newsome --- src/target/riscv/riscv-011.c | 11 +++++++---- src/target/riscv/riscv-013.c | 13 ++++++++----- src/target/riscv/riscv.c | 26 ++++++++++++++------------ src/target/riscv/riscv.h | 12 ++++++------ 4 files changed, 35 insertions(+), 27 deletions(-) diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index ae0b6e481..e2ae5b51a 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -227,10 +227,10 @@ static int get_register(struct target *target, riscv_reg_t *value, int regid); static riscv011_info_t *get_info(const struct target *target) { - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; assert(info); assert(info->version_specific); - return (riscv011_info_t *) info->version_specific; + return info->version_specific; } static unsigned int slot_offset(const struct target *target, slot_t slot) @@ -1408,7 +1408,10 @@ static int halt(struct target *target) static void deinit_target(struct target *target) { LOG_DEBUG("riscv_deinit_target()"); - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; + if (!info) + return; + free(info->version_specific); info->version_specific = NULL; } @@ -1549,7 +1552,7 @@ static int examine(struct target *target) uint32_t word0 = cache_get32(target, 0); uint32_t word1 = cache_get32(target, 1); - riscv_info_t *generic_info = (riscv_info_t *) target->arch_info; + struct riscv_info *generic_info = riscv_info(target); if (word0 == 1 && word1 == 0) { generic_info->xlen = 32; } else if (word0 == 0xffffffff && word1 == 3) { diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 1b1450a7d..b666f5246 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -34,7 +34,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target, bool step, bool use_hasel); static void riscv013_clear_abstract_error(struct target *target); -/* Implementations of the functions in riscv_info_t. */ +/* Implementations of the functions in struct riscv_info. */ static int riscv013_get_register(struct target *target, riscv_reg_t *value, int rid); static int riscv013_set_register(struct target *target, int regid, uint64_t value); @@ -225,10 +225,10 @@ LIST_HEAD(dm_list); static riscv013_info_t *get_info(const struct target *target) { - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; assert(info); assert(info->version_specific); - return (riscv013_info_t *) info->version_specific; + return info->version_specific; } /** @@ -1524,7 +1524,10 @@ static int wait_for_authbusy(struct target *target, uint32_t *dmstatus) static void deinit_target(struct target *target) { LOG_DEBUG("riscv_deinit_target()"); - riscv_info_t *info = (riscv_info_t *) target->arch_info; + struct riscv_info *info = target->arch_info; + if (!info) + return; + free(info->version_specific); /* TODO: free register arch_info */ info->version_specific = NULL; @@ -4173,7 +4176,7 @@ static int select_prepped_harts(struct target *target, bool *use_hasel) unsigned total_selected = 0; list_for_each_entry(entry, &dm->target_list, list) { struct target *t = entry->target; - riscv_info_t *r = riscv_info(t); + struct riscv_info *r = riscv_info(t); riscv013_info_t *info = get_info(t); unsigned index = info->index; LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index f79239a9d..eccceade1 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -405,13 +405,12 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out) static struct target_type *get_target_type(struct target *target) { - riscv_info_t *info = (riscv_info_t *) target->arch_info; - - if (!info) { + if (!target->arch_info) { LOG_ERROR("Target has not been initialized"); return NULL; } + RISCV_INFO(info); switch (info->dtm_version) { case 0: return &riscv011_target; @@ -426,7 +425,7 @@ static struct target_type *get_target_type(struct target *target) static int riscv_create_target(struct target *target, Jim_Interp *interp) { LOG_DEBUG("riscv_create_target()"); - target->arch_info = calloc(1, sizeof(riscv_info_t)); + target->arch_info = calloc(1, sizeof(struct riscv_info)); if (!target->arch_info) { LOG_ERROR("Failed to allocate RISC-V target structure."); return ERROR_FAIL; @@ -489,14 +488,17 @@ static void riscv_deinit_target(struct target *target) { LOG_DEBUG("riscv_deinit_target()"); - riscv_info_t *info = target->arch_info; + struct riscv_info *info = target->arch_info; struct target_type *tt = get_target_type(target); - if (tt && info->version_specific) + if (tt && info && info->version_specific) tt->deinit_target(target); riscv_free_registers(target); + if (!info) + return; + range_list_t *entry, *tmp; list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) { free(entry->name); @@ -1200,7 +1202,7 @@ int riscv_halt_go_all_harts(struct target *target) int halt_go(struct target *target) { - riscv_info_t *r = riscv_info(target); + RISCV_INFO(r); int result; if (!r->is_halted) { struct target_type *tt = get_target_type(target); @@ -1242,7 +1244,7 @@ int riscv_halt(struct target *target) foreach_smp_target(tlist, target->smp_targets) { struct target *t = tlist->target; - riscv_info_t *i = riscv_info(t); + struct riscv_info *i = riscv_info(t); if (i->prepped) { if (halt_go(t) != ERROR_OK) result = ERROR_FAIL; @@ -1434,7 +1436,7 @@ static int resume_prep(struct target *target, int current, static int resume_go(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution) { - riscv_info_t *r = riscv_info(target); + RISCV_INFO(r); int result; if (!r->is_halted) { struct target_type *tt = get_target_type(target); @@ -1483,7 +1485,7 @@ int riscv_resume( foreach_smp_target_direction(resume_order == RO_NORMAL, tlist, target->smp_targets) { struct target *t = tlist->target; - riscv_info_t *i = riscv_info(t); + struct riscv_info *i = riscv_info(t); if (i->prepped) { if (resume_go(t, current, address, handle_breakpoints, debug_execution) != ERROR_OK) @@ -2189,7 +2191,7 @@ int riscv_openocd_poll(struct target *target) struct target_list *list; foreach_smp_target(list, target->smp_targets) { struct target *t = list->target; - riscv_info_t *r = riscv_info(t); + struct riscv_info *r = riscv_info(t); enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid); switch (out) { case RPH_NO_CHANGE: @@ -3197,7 +3199,7 @@ struct target_type riscv_target = { /*** RISC-V Interface ***/ -void riscv_info_init(struct target *target, riscv_info_t *r) +void riscv_info_init(struct target *target, struct riscv_info *r) { memset(r, 0, sizeof(*r)); r->dtm_version = 1; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index a6d27f79b..efbd71c32 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -85,7 +85,7 @@ typedef struct { char *name; } range_list_t; -typedef struct { +struct riscv_info { unsigned dtm_version; struct command_context *cmd_ctx; @@ -225,7 +225,7 @@ typedef struct { riscv_sample_config_t sample_config; struct riscv_sample_buf sample_buf; -} riscv_info_t; +}; COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key, unsigned int value); @@ -261,13 +261,13 @@ extern bool riscv_ebreaku; /* Everything needs the RISC-V specific info structure, so here's a nice macro * that provides that. */ -static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused)); -static inline riscv_info_t *riscv_info(const struct target *target) +static inline struct riscv_info *riscv_info(const struct target *target) __attribute__((unused)); +static inline struct riscv_info *riscv_info(const struct target *target) { assert(target->arch_info); return target->arch_info; } -#define RISCV_INFO(R) riscv_info_t *R = riscv_info(target); +#define RISCV_INFO(R) struct riscv_info *R = riscv_info(target); extern uint8_t ir_dtmcontrol[4]; extern struct scan_field select_dtmcontrol; @@ -313,7 +313,7 @@ int riscv_openocd_deassert_reset(struct target *target); /*** RISC-V Interface ***/ /* Initializes the shared RISC-V structure. */ -void riscv_info_init(struct target *target, riscv_info_t *r); +void riscv_info_init(struct target *target, struct riscv_info *r); /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS * then the only hart. */