arm_adi_v5: Make the DAP API stateless
Remove entirely the concept of a "selected" AP that has to be maintained between calls. All the information the DAP ops need are now provided to each call through the AP/DAP pointer. Consolidate the cache of the SELECT fields into one single field caching the entire register. Change-Id: I2e1c93ac5ee8ac38a7d680ca2c660c30093a6b87 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3165 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Andreas Fritiofson
parent
54e89cae84
commit
830d0c55c0
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@ -75,11 +75,13 @@ static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
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* @param outvalue points to a 32-bit (little-endian) integer
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* @param invalue NULL, or points to a 32-bit (little-endian) integer
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* @param ack points to where the three bit JTAG_ACK_* code will be stored
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* @param memaccess_tck number of idle cycles to add after AP access
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*/
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static int adi_jtag_dp_scan(struct adiv5_dap *dap,
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uint8_t instr, uint8_t reg_addr, uint8_t RnW,
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uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
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uint8_t *outvalue, uint8_t *invalue, uint8_t *ack,
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uint32_t memaccess_tck)
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{
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struct jtag_tap *tap = dap->tap;
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struct scan_field fields[2];
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@ -117,9 +119,8 @@ static int adi_jtag_dp_scan(struct adiv5_dap *dap,
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if ((instr == JTAG_DP_APACC)
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&& ((reg_addr == MEM_AP_REG_DRW)
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|| ((reg_addr & 0xF0) == MEM_AP_REG_BD0))
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&& (dap->ap[dap_ap_get_select(dap)].memaccess_tck != 0))
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jtag_add_runtest(dap->ap[dap_ap_get_select(dap)].memaccess_tck,
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TAP_IDLE);
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&& memaccess_tck != 0)
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jtag_add_runtest(memaccess_tck, TAP_IDLE);
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return ERROR_OK;
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}
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@ -132,7 +133,8 @@ static int adi_jtag_dp_scan(struct adiv5_dap *dap,
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*/
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static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
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uint8_t instr, uint8_t reg_addr, uint8_t RnW,
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uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
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uint32_t outvalue, uint32_t *invalue, uint8_t *ack,
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uint32_t memaccess_tck)
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{
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uint8_t out_value_buf[4];
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int retval;
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@ -140,7 +142,7 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
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buf_set_u32(out_value_buf, 0, 32, outvalue);
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retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
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out_value_buf, (uint8_t *)invalue, ack);
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out_value_buf, (uint8_t *)invalue, ack, memaccess_tck);
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if (retval != ERROR_OK)
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return retval;
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@ -154,22 +156,22 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
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/**
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* Utility to write AP registers.
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*/
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static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
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static inline int adi_jtag_ap_write_check(struct adiv5_ap *ap,
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uint8_t reg_addr, uint8_t *outvalue)
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{
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return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
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outvalue, NULL, NULL);
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return adi_jtag_dp_scan(ap->dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
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outvalue, NULL, NULL, ap->memaccess_tck);
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}
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static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
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uint8_t instr, uint8_t reg_addr, uint8_t RnW,
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uint32_t outvalue, uint32_t *invalue)
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uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck)
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{
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int retval;
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/* Issue the read or write */
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retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
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RnW, outvalue, NULL, NULL);
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RnW, outvalue, NULL, NULL, memaccess_tck);
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if (retval != ERROR_OK)
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return retval;
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@ -178,7 +180,7 @@ static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
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*/
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if ((RnW == DPAP_READ) && (invalue != NULL))
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retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
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DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
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DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack, 0);
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return retval;
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}
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@ -218,7 +220,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
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* but collect its ACK status.
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*/
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retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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@ -254,7 +256,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
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}
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retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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@ -285,11 +287,11 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
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retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
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DP_CTRL_STAT, DPAP_WRITE,
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dap->dp_ctrl_stat | SSTICKYORUN
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| SSTICKYERR, NULL);
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| SSTICKYERR, NULL, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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@ -313,61 +315,61 @@ static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
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uint32_t *data)
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{
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return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
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reg, DPAP_READ, 0, data);
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reg, DPAP_READ, 0, data, 0);
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}
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static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
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uint32_t data)
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{
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return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
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reg, DPAP_WRITE, data, NULL);
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reg, DPAP_WRITE, data, NULL, 0);
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}
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/** Select the AP register bank matching bits 7:4 of reg. */
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static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
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static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
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{
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uint32_t select_ap_bank = reg & 0x000000F0;
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struct adiv5_dap *dap = ap->dap;
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uint32_t select = ((uint32_t)ap->ap_num << 24) | (reg & 0x000000F0);
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if (select_ap_bank == dap->ap_bank_value)
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if (select == dap->select)
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return ERROR_OK;
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dap->ap_bank_value = select_ap_bank;
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select_ap_bank |= dap->ap_current;
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dap->select = select;
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return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
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return jtag_dp_q_write(dap, DP_SELECT, select);
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}
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static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
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static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
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uint32_t *data)
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{
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int retval = jtag_ap_q_bankselect(dap, reg);
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int retval = jtag_ap_q_bankselect(ap, reg);
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if (retval != ERROR_OK)
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return retval;
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return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
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DPAP_READ, 0, data);
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return adi_jtag_scan_inout_check_u32(ap->dap, JTAG_DP_APACC, reg,
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DPAP_READ, 0, data, ap->memaccess_tck);
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}
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static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
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static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg,
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uint32_t data)
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{
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uint8_t out_value_buf[4];
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int retval = jtag_ap_q_bankselect(dap, reg);
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int retval = jtag_ap_q_bankselect(ap, reg);
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if (retval != ERROR_OK)
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return retval;
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buf_set_u32(out_value_buf, 0, 32, data);
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return adi_jtag_ap_write_check(dap, reg, out_value_buf);
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return adi_jtag_ap_write_check(ap, reg, out_value_buf);
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}
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static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
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{
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/* for JTAG, this is the only valid ABORT register operation */
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return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
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0, DPAP_WRITE, 1, NULL, ack);
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0, DPAP_WRITE, 1, NULL, ack, 0);
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}
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static int jtag_dp_run(struct adiv5_dap *dap)
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@ -114,7 +114,7 @@ static int swd_connect(struct adiv5_dap *dap)
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/* Make sure we don't try to perform any other accesses before the DPIDR read. */
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dap->do_reconnect = false;
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dap->dp_bank_value = 0;
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dap->select = 0;
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swd_queue_dp_read(dap, DP_IDCODE, &idcode);
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@ -158,18 +158,19 @@ static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
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/** Select the DP register bank matching bits 7:4 of reg. */
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static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
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{
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uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
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if (reg == DP_SELECT)
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return;
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if (select_dp_bank == dap->dp_bank_value)
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uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
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uint32_t select = select_dp_bank
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| (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
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if (select == dap->select)
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return;
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dap->dp_bank_value = select_dp_bank;
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select_dp_bank |= dap->ap_current | dap->ap_bank_value;
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dap->select = select;
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swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
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swd_queue_dp_write(dap, DP_SELECT, select);
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}
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static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
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@ -206,49 +207,55 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
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}
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/** Select the AP register bank matching bits 7:4 of reg. */
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static void swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
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static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
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{
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uint32_t select_ap_bank = reg & 0x000000F0;
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struct adiv5_dap *dap = ap->dap;
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uint32_t select = ((uint32_t)ap->ap_num << 24)
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| (reg & 0x000000F0)
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| (dap->select & DP_SELECT_DPBANK);
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if (select_ap_bank == dap->ap_bank_value)
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if (select == dap->select)
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return;
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dap->ap_bank_value = select_ap_bank;
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select_ap_bank |= dap->ap_current | dap->dp_bank_value;
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dap->select = select;
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swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
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swd_queue_dp_write(dap, DP_SELECT, select);
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}
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static int swd_queue_ap_read(struct adiv5_dap *dap, unsigned reg,
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static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
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uint32_t *data)
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{
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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struct adiv5_dap *dap = ap->dap;
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int retval = swd_check_reconnect(dap);
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if (retval != ERROR_OK)
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return retval;
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swd_queue_ap_bankselect(dap, reg);
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swd->read_reg(swd_cmd(true, true, reg), dap->last_read, dap->ap[dap_ap_get_select(dap)].memaccess_tck);
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swd_queue_ap_bankselect(ap, reg);
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swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
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dap->last_read = data;
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return check_sync(dap);
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}
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static int swd_queue_ap_write(struct adiv5_dap *dap, unsigned reg,
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static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
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uint32_t data)
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{
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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struct adiv5_dap *dap = ap->dap;
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int retval = swd_check_reconnect(dap);
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if (retval != ERROR_OK)
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return retval;
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swd_finish_read(dap);
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swd_queue_ap_bankselect(dap, reg);
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swd->write_reg(swd_cmd(false, true, reg), data, dap->ap[dap_ap_get_select(dap)].memaccess_tck);
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swd_queue_ap_bankselect(ap, reg);
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swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
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return check_sync(dap);
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}
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@ -94,28 +94,6 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address
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* *
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***************************************************************************/
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/**
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* Select one of the APs connected to the specified DAP. The
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* selection is implicitly used with future AP transactions.
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* This is a NOP if the specified AP is already selected.
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*
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* @param dap The DAP
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* @param apsel Number of the AP to (implicitly) use with further
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* transactions. This normally identifies a MEM-AP.
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*/
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void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
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{
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uint32_t new_ap = (ap << 24) & 0xFF000000;
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if (new_ap != dap->ap_current) {
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dap->ap_current = new_ap;
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/* Switching AP invalidates cached values.
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* Values MUST BE UPDATED BEFORE AP ACCESS.
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*/
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dap->ap_bank_value = -1;
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}
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}
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static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
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{
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csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
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@ -608,9 +586,6 @@ struct adiv5_dap *dap_init(void)
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/* Number of bits for tar autoincrement, impl. dep. at least 10 */
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dap->ap[i].tar_autoincr_block = (1<<10);
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}
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dap->ap_current = -1;
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dap->ap_bank_value = -1;
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dap->dp_bank_value = -1;
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return dap;
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}
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@ -633,15 +608,12 @@ int dap_dp_init(struct adiv5_dap *dap)
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if (!dap->ops)
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dap->ops = &jtag_dp_ops;
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dap->ap_current = -1;
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dap->ap_bank_value = -1;
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dap->select = DP_SELECT_INVALID;
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dap->last_read = NULL;
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for (size_t i = 0; i < 10; i++) {
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/* DP initialization */
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dap->dp_bank_value = 0;
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retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
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if (retval != ERROR_OK)
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continue;
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@ -131,6 +131,11 @@
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#define IDR_JEP106_ARM 0x04760000
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#define DP_SELECT_APSEL 0xFF000000
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#define DP_SELECT_APBANK 0x000000F0
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#define DP_SELECT_DPBANK 0x0000000F
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#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
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/**
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* This represents an ARM Debug Interface (v5) Access Port (AP).
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* Most common is a MEM-AP, for memory access.
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@ -211,27 +216,10 @@ struct adiv5_dap {
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uint32_t apsel;
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/**
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* Cache for DP_SELECT bits identifying the current AP. A DAP may
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* connect to multiple APs, such as one MEM-AP for general access,
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* another reserved for accessing debug modules, and a JTAG-DP.
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* "-1" indicates no cached value.
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* Cache for DP_SELECT register. A value of DP_SELECT_INVALID
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* indicates no cached value and forces rewrite of the register.
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*/
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uint32_t ap_current;
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|
||||
/**
|
||||
* Cache for DP_SELECT bits identifying the current four-word AP
|
||||
* register bank. This caches AP register addresss bits 7:4; JTAG
|
||||
* and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
|
||||
* "-1" indicates no cached value.
|
||||
*/
|
||||
uint32_t ap_bank_value;
|
||||
|
||||
/**
|
||||
* Cache for DP_SELECT bits identifying the current four-word DP
|
||||
* register bank. This caches DP register addresss bits 7:4; JTAG
|
||||
* and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
|
||||
*/
|
||||
uint32_t dp_bank_value;
|
||||
uint32_t select;
|
||||
|
||||
/* information about current pending SWjDP-AHBAP transaction */
|
||||
uint8_t ack;
|
||||
|
|
@ -271,10 +259,10 @@ struct dap_ops {
|
|||
uint32_t data);
|
||||
|
||||
/** AP register read. */
|
||||
int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
|
||||
int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
|
||||
uint32_t *data);
|
||||
/** AP register write. */
|
||||
int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
|
||||
int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
|
||||
uint32_t data);
|
||||
|
||||
/** AP operation abort. */
|
||||
|
|
@ -302,9 +290,6 @@ enum ap_type {
|
|||
AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
|
||||
};
|
||||
|
||||
/* AP selection applies to future AP transactions */
|
||||
void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
|
||||
|
||||
/**
|
||||
* Queue a DP register read.
|
||||
* Note that not all DP registers are readable; also, that JTAG and SWD
|
||||
|
|
@ -356,8 +341,7 @@ static inline int dap_queue_ap_read(struct adiv5_ap *ap,
|
|||
unsigned reg, uint32_t *data)
|
||||
{
|
||||
assert(ap->dap->ops != NULL);
|
||||
dap_ap_select(ap->dap, ap->ap_num);
|
||||
return ap->dap->ops->queue_ap_read(ap->dap, reg, data);
|
||||
return ap->dap->ops->queue_ap_read(ap, reg, data);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -373,8 +357,7 @@ static inline int dap_queue_ap_write(struct adiv5_ap *ap,
|
|||
unsigned reg, uint32_t data)
|
||||
{
|
||||
assert(ap->dap->ops != NULL);
|
||||
dap_ap_select(ap->dap, ap->ap_num);
|
||||
return ap->dap->ops->queue_ap_write(ap->dap, reg, data);
|
||||
return ap->dap->ops->queue_ap_write(ap, reg, data);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -451,12 +434,6 @@ static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
|
|||
}
|
||||
}
|
||||
|
||||
/** Accessor for currently selected DAP-AP number (0..255) */
|
||||
static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
|
||||
{
|
||||
return (uint8_t)(swjdp->ap_current >> 24);
|
||||
}
|
||||
|
||||
/* Queued MEM-AP memory mapped single word transfers. */
|
||||
int mem_ap_read_u32(struct adiv5_ap *ap,
|
||||
uint32_t address, uint32_t *value);
|
||||
|
|
|
|||
Loading…
Reference in New Issue