target/cortex_m: faster reading of all CPU registers
Without the change cortex_m_debug_entry() reads all registers calling cortex_m_load_core_reg_u32() for each register with a poor usage of JTAG/SWD queue. It is time consuming, especially on an USB FS based adapter. Moreover if target_request debugmsgs are enabled, DCB_DCRDR is saved and restored on each register read. This change introduces cortex_m_fast_read_all_regs() which queues all register reads and a single dap_run() transaction does all work. cortex_m_fast_read_all_regs() reads all registers unconditionally regardless register cache is valid or not. This is a difference from the original cortex_m_debug_entry() code. cortex_m_debug_entry times from -d3 log, Cortex-M4F and CMSIS-DAP (Kinetis K28F-FRDM kit) target_request | time [ms] debugmsgs | without the change | with the change ---------------+--------------------+----------------- disable | 186 | 27 enable | 232 | 29 Added checking of DHCSR.S_REGRDY flag. If "not ready" is seen, cortex_m->slow_register_read is set and fallback to the old register read method cortex_m_slow_read_all_regs() is used instead of cortex_m_fast_read_all_regs(). Change-Id: I0665d94b97ede217394640871dc451ec93410254 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/5321 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek
parent
65d7629183
commit
88f429ead0
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@ -251,7 +251,7 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
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return ERROR_OK;
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}
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static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
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uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
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{
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switch (arm_reg_id) {
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case ARMV7M_R0 ... ARMV7M_R14:
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@ -289,7 +289,7 @@ static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
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}
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}
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static bool armv7m_map_reg_packing(unsigned int arm_reg_id,
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bool armv7m_map_reg_packing(unsigned int arm_reg_id,
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unsigned int *reg32_id, uint32_t *offset)
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{
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@ -309,6 +309,11 @@ int armv7m_invalidate_core_regs(struct target *target);
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int armv7m_restore_context(struct target *target);
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uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id);
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bool armv7m_map_reg_packing(unsigned int arm_reg_id,
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unsigned int *reg32_id, uint32_t *offset);
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int armv7m_checksum_memory(struct target *target,
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target_addr_t address, uint32_t count, uint32_t *checksum);
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int armv7m_blank_check_memory(struct target *target,
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@ -202,6 +202,163 @@ static int cortex_m_load_core_reg_u32(struct target *target,
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return retval;
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}
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static int cortex_m_slow_read_all_regs(struct target *target)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
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for (unsigned int reg_id = 0; reg_id < num_regs; reg_id++) {
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struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
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if (r->exist) {
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int retval = armv7m->arm.read_core_reg(target, r, reg_id, ARM_MODE_ANY);
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if (retval != ERROR_OK)
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return retval;
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}
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}
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return ERROR_OK;
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}
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static int cortex_m_queue_reg_read(struct target *target, uint32_t regsel,
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uint32_t *reg_value, uint32_t *dhcsr)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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int retval;
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retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR, dhcsr);
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if (retval != ERROR_OK)
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return retval;
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return mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, reg_value);
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}
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static int cortex_m_fast_read_all_regs(struct target *target)
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{
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struct cortex_m_common *cortex_m = target_to_cm(target);
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struct armv7m_common *armv7m = target_to_armv7m(target);
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int retval;
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uint32_t dcrdr;
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/* because the DCB_DCRDR is used for the emulated dcc channel
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* we have to save/restore the DCB_DCRDR when used */
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if (target->dbg_msg_enabled) {
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retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
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if (retval != ERROR_OK)
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return retval;
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}
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const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
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const unsigned int n_r32 = ARMV7M_LAST_REG - ARMV7M_CORE_FIRST_REG + 1
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+ ARMV7M_FPU_LAST_REG - ARMV7M_FPU_FIRST_REG + 1;
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/* we need one 32-bit word for each register except FP D0..D15, which
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* need two words */
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uint32_t r_vals[n_r32];
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uint32_t dhcsr[n_r32];
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unsigned int wi = 0; /* write index to r_vals and dhcsr arrays */
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unsigned int reg_id; /* register index in the reg_list, ARMV7M_R0... */
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for (reg_id = 0; reg_id < num_regs; reg_id++) {
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struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
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if (!r->exist)
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continue; /* skip non existent registers */
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if (r->size <= 8) {
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/* Any 8-bit or shorter register is unpacked from a 32-bit
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* container register. Skip it now. */
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continue;
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}
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uint32_t regsel = armv7m_map_id_to_regsel(reg_id);
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retval = cortex_m_queue_reg_read(target, regsel, &r_vals[wi],
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&dhcsr[wi]);
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if (retval != ERROR_OK)
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return retval;
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wi++;
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assert(r->size == 32 || r->size == 64);
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if (r->size == 32)
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continue; /* done with 32-bit register */
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assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
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/* the odd part of FP register (S1, S3...) */
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retval = cortex_m_queue_reg_read(target, regsel + 1, &r_vals[wi],
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&dhcsr[wi]);
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if (retval != ERROR_OK)
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return retval;
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wi++;
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}
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assert(wi <= n_r32);
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retval = dap_run(armv7m->debug_ap->dap);
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if (retval != ERROR_OK)
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return retval;
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if (target->dbg_msg_enabled) {
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/* restore DCB_DCRDR - this needs to be in a separate
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* transaction otherwise the emulated DCC channel breaks */
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retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
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if (retval != ERROR_OK)
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return retval;
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}
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bool not_ready = false;
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for (unsigned int i = 0; i < wi; i++) {
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if ((dhcsr[i] & S_REGRDY) == 0) {
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not_ready = true;
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LOG_DEBUG("Register %u was not ready during fast read", i);
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}
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cortex_m_cumulate_dhcsr_sticky(cortex_m, dhcsr[i]);
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}
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if (not_ready) {
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/* Any register was not ready,
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* fall back to slow read with S_REGRDY polling */
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return ERROR_TIMEOUT_REACHED;
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}
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LOG_DEBUG("read %u 32-bit registers", wi);
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unsigned int ri = 0; /* read index from r_vals array */
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for (reg_id = 0; reg_id < num_regs; reg_id++) {
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struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
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if (!r->exist)
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continue; /* skip non existent registers */
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r->dirty = false;
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unsigned int reg32_id;
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uint32_t offset;
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if (armv7m_map_reg_packing(reg_id, ®32_id, &offset)) {
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/* Unpack a partial register from 32-bit container register */
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struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
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/* The container register ought to precede all regs unpacked
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* from it in the reg_list. So the value should be ready
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* to unpack */
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assert(r32->valid);
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buf_cpy(r32->value + offset, r->value, r->size);
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} else {
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assert(r->size == 32 || r->size == 64);
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buf_set_u32(r->value, 0, 32, r_vals[ri++]);
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if (r->size == 64) {
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assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
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/* the odd part of FP register (S1, S3...) */
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buf_set_u32(r->value + 4, 0, 32, r_vals[ri++]);
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}
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}
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r->valid = true;
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}
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assert(ri == wi);
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return retval;
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}
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static int cortex_m_store_core_reg_u32(struct target *target,
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uint32_t regsel, uint32_t value)
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{
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@ -610,7 +767,6 @@ static int cortex_m_examine_exception_reason(struct target *target)
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static int cortex_m_debug_entry(struct target *target)
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{
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int i;
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uint32_t xPSR;
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int retval;
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struct cortex_m_common *cortex_m = target_to_cm(target);
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@ -646,16 +802,21 @@ static int cortex_m_debug_entry(struct target *target)
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secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
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}
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/* Examine target state and mode
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* First load register accessible through core debug port */
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int num_regs = arm->core_cache->num_regs;
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for (i = 0; i < num_regs; i++) {
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r = &armv7m->arm.core_cache->reg_list[i];
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if (r->exist && !r->valid)
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arm->read_core_reg(target, r, i, ARM_MODE_ANY);
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/* Load all registers to arm.core_cache */
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if (!cortex_m->slow_register_read) {
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retval = cortex_m_fast_read_all_regs(target);
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if (retval == ERROR_TIMEOUT_REACHED) {
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cortex_m->slow_register_read = true;
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LOG_DEBUG("Switched to slow register read");
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}
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}
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if (cortex_m->slow_register_read)
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retval = cortex_m_slow_read_all_regs(target);
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if (retval != ERROR_OK)
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return retval;
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r = arm->cpsr;
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xPSR = buf_get_u32(r->value, 0, 32);
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@ -238,6 +238,8 @@ struct cortex_m_common {
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const struct cortex_m_part_info *core_info;
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struct armv7m_common armv7m;
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bool slow_register_read; /* A register has not been ready, poll S_REGRDY */
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int apsel;
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/* Whether this target has the erratum that makes C_MASKINTS not apply to
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