flash Kinetis: add KL28 device
This device differs a lot from others in KL series. Unfortunately the System Integration Module, where device identification resides, moved to a new address so probe now have to try both addresses of SIM_SDID. Introduce a new bank creation option: -sim-base to ensure error free probe. WDOG32 is slightly different from KE1x and on different address. System Mode Controler changed layout to word aligned. Change-Id: I2c9dca0c4ad4228fcc941d6078d15f5e394833ff Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4059 Tested-by: jenkins Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Tomas Vanek
Freddie Chopin
parent
5a2608bbbc
commit
8dcb91fb83
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@ -5368,6 +5368,11 @@ recognizes flash size and a number of flash banks (1-4) using the chip
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identification register, and autoconfigures itself.
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Use kinetis_ke driver for KE0x devices.
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The @var{kinetis} driver defines option:
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@itemize
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@item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
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@end itemize
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@example
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flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
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@end example
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@ -96,19 +96,25 @@
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#define FTFx_FCCOB3 0x40020004
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#define FTFx_FPROT3 0x40020010
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#define FTFx_FDPROT 0x40020017
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#define SIM_SDID 0x40048024
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#define SIM_SOPT1 0x40047000
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#define SIM_FCFG1 0x4004804c
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#define SIM_FCFG2 0x40048050
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#define SIM_BASE 0x40047000
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#define SIM_BASE_KL28 0x40074000
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#define SIM_COPC 0x40048100
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/* SIM_COPC does not exist on devices with changed SIM_BASE */
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#define WDOG_BASE 0x40052000
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#define WDOG32_KE1X 0x40052000
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#define WDOG32_KL28 0x40076000
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#define SMC_PMCTRL 0x4007E001
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#define SMC_PMSTAT 0x4007E003
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#define SMC32_PMCTRL 0x4007E00C
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#define SMC32_PMSTAT 0x4007E014
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#define MCM_PLACR 0xF000300C
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/* Offsets */
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#define SIM_SOPT1_OFFSET 0x0000
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#define SIM_SDID_OFFSET 0x1024
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#define SIM_FCFG1_OFFSET 0x104c
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#define SIM_FCFG2_OFFSET 0x1050
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#define WDOG_STCTRLH_OFFSET 0
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#define WDOG32_CS_OFFSET 0
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@ -272,6 +278,7 @@ struct kinetis_chip {
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uint32_t dflash_size; /* accessible rest of FlexNVM if EEPROM backup uses part of FlexNVM */
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uint32_t progr_accel_ram;
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uint32_t sim_base;
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enum {
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FS_PROGRAM_SECTOR = 1,
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@ -297,6 +304,11 @@ struct kinetis_chip {
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KINETIS_WDOG32_KL28,
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} watchdog_type;
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enum {
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KINETIS_SMC,
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KINETIS_SMC32,
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} sysmodectrlr_type;
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char name[40];
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unsigned num_banks;
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@ -844,11 +856,25 @@ static struct kinetis_chip *kinetis_get_chip(struct target *target)
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return NULL;
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}
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static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const char *argv[])
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{
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int i;
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for (i = 0; i < argc; i++) {
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if (strcmp(argv[i], "-sim-base") == 0) {
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if (i + 1 < argc)
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k_chip->sim_base = strtoul(argv[++i], NULL, 0);
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} else
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LOG_ERROR("Unsupported flash bank option %s", argv[i]);
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}
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return ERROR_OK;
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}
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FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
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{
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struct target *target = bank->target;
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struct kinetis_chip *k_chip;
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struct kinetis_flash_bank *k_bank;
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int retval;
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if (CMD_ARGC < 6)
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return ERROR_COMMAND_SYNTAX_ERROR;
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@ -865,6 +891,11 @@ FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
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}
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k_chip->target = target;
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/* only the first defined bank can define chip options */
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retval = kinetis_chip_options(k_chip, CMD_ARGC - 6, CMD_ARGV + 6);
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if (retval != ERROR_OK)
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return retval;
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}
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if (k_chip->num_banks >= KINETIS_MAX_BANKS) {
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@ -1467,17 +1498,44 @@ static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t fa
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}
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static int kinetis_check_run_mode(struct target *target)
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static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
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{
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int result;
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uint32_t stat32;
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struct target *target = k_chip->target;
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switch (k_chip->sysmodectrlr_type) {
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case KINETIS_SMC:
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result = target_read_u8(target, SMC_PMSTAT, pmstat);
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return result;
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case KINETIS_SMC32:
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result = target_read_u32(target, SMC32_PMSTAT, &stat32);
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if (result == ERROR_OK)
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*pmstat = stat32 & 0xff;
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return result;
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}
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return ERROR_FAIL;
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}
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static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
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{
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int result, i;
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uint8_t pmctrl, pmstat;
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uint8_t pmstat;
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struct target *target;
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if (k_chip == NULL) {
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LOG_ERROR("Chip not probed.");
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return ERROR_FAIL;
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}
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target = k_chip->target;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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result = target_read_u8(target, SMC_PMSTAT, &pmstat);
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result = kinetis_read_pmstat(k_chip, &pmstat);
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if (result != ERROR_OK)
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return result;
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@ -1487,13 +1545,21 @@ static int kinetis_check_run_mode(struct target *target)
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if (pmstat == PM_STAT_VLPR) {
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/* It is safe to switch from VLPR to RUN mode without changing clock */
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LOG_INFO("Switching from VLPR to RUN mode.");
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pmctrl = PM_CTRL_RUNM_RUN;
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result = target_write_u8(target, SMC_PMCTRL, pmctrl);
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switch (k_chip->sysmodectrlr_type) {
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case KINETIS_SMC:
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result = target_write_u8(target, SMC_PMCTRL, PM_CTRL_RUNM_RUN);
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break;
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case KINETIS_SMC32:
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result = target_write_u32(target, SMC32_PMCTRL, PM_CTRL_RUNM_RUN);
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break;
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}
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if (result != ERROR_OK)
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return result;
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for (i = 100; i; i--) {
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result = target_read_u8(target, SMC_PMSTAT, &pmstat);
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result = kinetis_read_pmstat(k_chip, &pmstat);
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if (result != ERROR_OK)
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return result;
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@ -1539,8 +1605,9 @@ static int kinetis_erase(struct flash_bank *bank, int first, int last)
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{
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int result, i;
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struct kinetis_flash_bank *k_bank = bank->driver_priv;
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struct kinetis_chip *k_chip = k_bank->k_chip;
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result = kinetis_check_run_mode(bank->target);
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result = kinetis_check_run_mode(k_chip);
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if (result != ERROR_OK)
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return result;
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@ -1816,8 +1883,9 @@ static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
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bool set_fcf = false;
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int sect = 0;
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struct kinetis_flash_bank *k_bank = bank->driver_priv;
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struct kinetis_chip *k_chip = k_bank->k_chip;
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result = kinetis_check_run_mode(bank->target);
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result = kinetis_check_run_mode(k_chip);
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if (result != ERROR_OK)
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return result;
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@ -1902,7 +1970,18 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
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name[0] = '\0';
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result = target_read_u32(target, SIM_SDID, &k_chip->sim_sdid);
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if (k_chip->sim_base)
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result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
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else {
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result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
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if (result == ERROR_OK)
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k_chip->sim_base = SIM_BASE;
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else {
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result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
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if (result == ERROR_OK)
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k_chip->sim_base = SIM_BASE_KL28;
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}
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}
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if (result != ERROR_OK)
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return result;
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@ -2004,7 +2083,7 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
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case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
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/* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
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uint32_t sopt1;
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result = target_read_u32(target, SIM_SOPT1, &sopt1);
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result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
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if (result != ERROR_OK)
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return result;
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@ -2112,8 +2191,21 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
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k_chip->watchdog_type = KINETIS_WDOG_COP;
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cpu_mhz = 48;
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if (subfamid == 3 && (familyid == 1 || familyid == 2))
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switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
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case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX3:
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case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX3:
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subfamid = 7;
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break;
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case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
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cpu_mhz = 72;
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k_chip->pflash_sector_size = 2<<10;
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num_blocks = 2;
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k_chip->watchdog_type = KINETIS_WDOG32_KL28;
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k_chip->sysmodectrlr_type = KINETIS_SMC32;
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break;
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}
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snprintf(name, sizeof(name), "MKL%u%uZ%%s%u",
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familyid, subfamid, cpu_mhz / 10);
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break;
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@ -2234,11 +2326,11 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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result = target_read_u32(target, SIM_FCFG1, &k_chip->sim_fcfg1);
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result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
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if (result != ERROR_OK)
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return result;
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result = target_read_u32(target, SIM_FCFG2, &k_chip->sim_fcfg2);
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result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
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if (result != ERROR_OK)
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return result;
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@ -2573,7 +2665,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
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int result;
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/* suprisingly blank check does not work in VLPR and HSRUN modes */
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result = kinetis_check_run_mode(bank->target);
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result = kinetis_check_run_mode(k_chip);
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if (result != ERROR_OK)
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return result;
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@ -2653,6 +2745,8 @@ COMMAND_HANDLER(kinetis_nvm_partition)
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struct kinetis_chip *k_chip;
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uint32_t sim_fcfg1;
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k_chip = kinetis_get_chip(target);
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if (CMD_ARGC >= 2) {
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if (strcmp(CMD_ARGV[0], "dataflash") == 0)
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sz_type = DF_SIZE;
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@ -2665,7 +2759,11 @@ COMMAND_HANDLER(kinetis_nvm_partition)
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}
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switch (sz_type) {
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case SHOW_INFO:
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result = target_read_u32(target, SIM_FCFG1, &sim_fcfg1);
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if (k_chip == NULL) {
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LOG_ERROR("Chip not probed.");
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return ERROR_FAIL;
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}
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result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
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if (result != ERROR_OK)
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return result;
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@ -2748,7 +2846,7 @@ COMMAND_HANDLER(kinetis_nvm_partition)
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LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
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flex_nvm_partition_code, ee_size_code);
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result = kinetis_check_run_mode(target);
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result = kinetis_check_run_mode(k_chip);
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if (result != ERROR_OK)
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return result;
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@ -2765,7 +2863,6 @@ COMMAND_HANDLER(kinetis_nvm_partition)
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command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
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k_chip = kinetis_get_chip(target);
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if (k_chip) {
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first_nvm_bank = k_chip->num_pflash_blocks;
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num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
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