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target: consolidate existing target/algo common_magic 

Unify common_magic type to unsigned int
Move common_magic to be the first member of the struct
Add unsigned specifier to xxx_COMMON_MAGIC #defines

Change-Id: If961d33232698529514ba3720e04418baf6dc6fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6996
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek 2022-05-26 10:01:45 +02:00
parent b76a7a82b2
commit 8f299c6aec
23 changed files with 67 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/target/aarch64.h
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@ -9,7 +9,7 @@
#include "armv8.h"
#define AARCH64_COMMON_MAGIC 0x411fc082
#define AARCH64_COMMON_MAGIC 0x411fc082U
#define CPUDBG_CPUID 0xD00
#define CPUDBG_CTYPR 0xD04
@ -38,7 +38,7 @@ struct aarch64_brp {
};
struct aarch64_common {
int common_magic;
unsigned int common_magic;
/* Context information */
uint32_t system_control_reg;

4
src/target/arc.h
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@ -27,7 +27,7 @@
#include "arc_cmd.h"
#include "arc_mem.h"
#define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */
#define ARC_COMMON_MAGIC 0xB32EB324U /* just a unique number */
#define AUX_DEBUG_REG 0x5
#define AUX_PC_REG 0x6
@ -183,7 +183,7 @@ struct arc_actionpoint {
};
struct arc_common {
uint32_t common_magic;
unsigned int common_magic;
struct arc_jtag jtag_info;

7
src/target/arm.h
View File

@ -155,7 +155,7 @@ enum arm_vfp_version {
ARM_VFP_V3,
};
#define ARM_COMMON_MAGIC 0x0A450A45
#define ARM_COMMON_MAGIC 0x0A450A45U
/**
* Represents a generic ARM core, with standard application registers.
@ -165,7 +165,8 @@ enum arm_vfp_version {
* registers as traditional ARM cores, and only support Thumb2 instructions.
*/
struct arm {
int common_magic;
unsigned int common_magic;
struct reg_cache *core_cache;
/** Handle to the PC; valid in all core modes. */
@ -252,7 +253,7 @@ static inline bool is_arm(struct arm *arm)
}
struct arm_algorithm {
int common_magic;
unsigned int common_magic;
enum arm_mode core_mode;
enum arm_state core_state;

5
src/target/arm720t.h
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@ -11,11 +11,12 @@
#include "arm7tdmi.h"
#include "armv4_5_mmu.h"
#define ARM720T_COMMON_MAGIC 0xa720a720
#define ARM720T_COMMON_MAGIC 0xa720a720U
struct arm720t_common {
unsigned int common_magic;
struct arm7_9_common arm7_9_common;
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
uint32_t cp15_control_reg;
uint32_t fsr_reg;

5
src/target/arm7_9_common.h
View File

@ -20,14 +20,15 @@
#include "arm.h"
#include "arm_jtag.h"
#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
#define ARM7_9_COMMON_MAGIC 0x0a790a79U /**< */
/**
* Structure for items that are common between both ARM7 and ARM9 targets.
*/
struct arm7_9_common {
unsigned int common_magic;
struct arm arm;
uint32_t common_magic;
struct arm_jtag jtag_info; /**< JTAG information for target */
struct reg_cache *eice_cache; /**< Embedded ICE register cache */

5
src/target/arm920t.h
View File

@ -11,11 +11,12 @@
#include "arm9tdmi.h"
#include "armv4_5_mmu.h"
#define ARM920T_COMMON_MAGIC 0xa920a920
#define ARM920T_COMMON_MAGIC 0xa920a920U
struct arm920t_common {
unsigned int common_magic;
struct arm7_9_common arm7_9_common;
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
uint32_t cp15_control_reg;
uint32_t d_fsr;

5
src/target/arm926ejs.h
View File

@ -11,11 +11,12 @@
#include "arm9tdmi.h"
#include "armv4_5_mmu.h"
#define ARM926EJS_COMMON_MAGIC 0xa926a926
#define ARM926EJS_COMMON_MAGIC 0xa926a926U
struct arm926ejs_common {
unsigned int common_magic;
struct arm7_9_common arm7_9_common;
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2,
uint32_t crn, uint32_t crm, uint32_t *value);

5
src/target/arm946e.h
View File

@ -16,11 +16,12 @@
#include "arm9tdmi.h"
#define ARM946E_COMMON_MAGIC 0x20f920f9
#define ARM946E_COMMON_MAGIC 0x20f920f9U
struct arm946e_common {
unsigned int common_magic;
struct arm7_9_common arm7_9_common;
int common_magic;
uint32_t cp15_control_reg;
uint32_t cp15_cache_info;
};

5
src/target/arm966e.h
View File

@ -13,11 +13,12 @@
#include "arm9tdmi.h"
#define ARM966E_COMMON_MAGIC 0x20f920f9
#define ARM966E_COMMON_MAGIC 0x20f920f9U
struct arm966e_common {
unsigned int common_magic;
struct arm7_9_common arm7_9_common;
int common_magic;
uint32_t cp15_control_reg;
};

5
src/target/armv7a.h
View File

@ -19,7 +19,7 @@ enum {
ARM_CPSR = 16
};
#define ARMV7_COMMON_MAGIC 0x0A450999
#define ARMV7_COMMON_MAGIC 0x0A450999U
/* VA to PA translation operations opc2 values*/
#define V2PCWPR 0
@ -87,8 +87,9 @@ struct armv7a_mmu_common {
};
struct armv7a_common {
unsigned int common_magic;
struct arm arm;
int common_magic;
struct reg_cache *core_cache;
/* Core Debug Unit */

7
src/target/armv7m.h
View File

@ -215,12 +215,13 @@ enum {
#define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
#define ARMV7M_COMMON_MAGIC 0x2A452A45
#define ARMV7M_COMMON_MAGIC 0x2A452A45U
struct armv7m_common {
unsigned int common_magic;
struct arm arm;
int common_magic;
int exception_number;
/* AP this processor is connected to in the DAP */
@ -289,7 +290,7 @@ target_to_armv7m_safe(struct target *target)
}
struct armv7m_algorithm {
int common_magic;
unsigned int common_magic;
enum arm_mode core_mode;

5
src/target/armv8.h
View File

@ -108,7 +108,7 @@ enum run_control_op {
ARMV8_RUNCONTROL_STEP = 3,
};
#define ARMV8_COMMON_MAGIC 0x0A450AAA
#define ARMV8_COMMON_MAGIC 0x0A450AAAU
/* VA to PA translation operations opc2 values*/
#define V2PCWPR 0
@ -178,8 +178,9 @@ struct armv8_mmu_common {
};
struct armv8_common {
unsigned int common_magic;
struct arm arm;
int common_magic;
struct reg_cache *core_cache;
/* Core Debug Unit */

6
src/target/avr32_ap7k.h
View File

@ -9,9 +9,11 @@
struct target;
#define AP7K_COMMON_MAGIC 0x4150374b
#define AP7K_COMMON_MAGIC 0x4150374bU
struct avr32_ap7k_common {
int common_magic;
unsigned int common_magic;
struct avr32_jtag jtag;
struct reg_cache *core_cache;
uint32_t core_regs[AVR32NUMCOREREGS];

4
src/target/cortex_a.h
View File

@ -19,7 +19,7 @@
#include "armv7a.h"
#define CORTEX_A_COMMON_MAGIC 0x411fc082
#define CORTEX_A_COMMON_MAGIC 0x411fc082U
#define CORTEX_A5_PARTNUM 0xc05
#define CORTEX_A7_PARTNUM 0xc07
@ -67,7 +67,7 @@ struct cortex_a_wrp {
};
struct cortex_a_common {
int common_magic;
unsigned int common_magic;
/* Context information */
uint32_t cpudbg_dscr;

4
src/target/cortex_m.h
View File

@ -17,7 +17,7 @@
#include "armv7m.h"
#include "helper/bits.h"
#define CORTEX_M_COMMON_MAGIC 0x1A451A45
#define CORTEX_M_COMMON_MAGIC 0x1A451A45U
#define SYSTEM_CONTROL_BASE 0x400FE000
@ -199,7 +199,7 @@ enum cortex_m_isrmasking_mode {
};
struct cortex_m_common {
int common_magic;
unsigned int common_magic;
/* Context information */
uint32_t dcb_dhcsr;

7
src/target/mips32.h
View File

@ -16,7 +16,7 @@
#include "target.h"
#include "mips32_pracc.h"
#define MIPS32_COMMON_MAGIC 0xB320B320
#define MIPS32_COMMON_MAGIC 0xB320B320U
/**
* Memory segments (32bit kernel mode addresses)
@ -82,7 +82,8 @@ struct mips32_comparator {
};
struct mips32_common {
uint32_t common_magic;
unsigned int common_magic;
void *arch_info;
struct reg_cache *core_cache;
struct mips_ejtag ejtag_info;
@ -119,7 +120,7 @@ struct mips32_core_reg {
};
struct mips32_algorithm {
int common_magic;
unsigned int common_magic;
enum mips32_isa_mode isa_mode;
};

5
src/target/mips64.h
View File

@ -19,7 +19,7 @@
#include "register.h"
#include "mips64_pracc.h"
#define MIPS64_COMMON_MAGIC 0xB640B640
#define MIPS64_COMMON_MAGIC 0xB640B640U
/* MIPS64 CP0 registers */
#define MIPS64_C0_INDEX 0
@ -81,7 +81,8 @@ struct mips64_comparator {
};
struct mips64_common {
uint32_t common_magic;
unsigned int common_magic;
void *arch_info;
struct reg_cache *core_cache;
struct mips_ejtag ejtag_info;

5
src/target/mips_m4k.h
View File

@ -15,10 +15,11 @@
struct target;
#define MIPSM4K_COMMON_MAGIC 0xB321B321
#define MIPSM4K_COMMON_MAGIC 0xB321B321U
struct mips_m4k_common {
uint32_t common_magic;
unsigned int common_magic;
bool is_pic32mx;
struct mips32_common mips32;
};

3
src/target/mips_mips64.h
View File

@ -17,7 +17,8 @@
#include "helper/types.h"
struct mips_mips64_common {
int common_magic;
unsigned int common_magic;
struct mips64_common mips64_common;
};

3
src/target/nds32.h
View File

@ -224,7 +224,8 @@ struct nds32_misc_config {
* Represents a generic Andes core.
*/
struct nds32 {
uint32_t common_magic;
unsigned int common_magic;
struct reg_cache *core_cache;
/** Handle for the debug module. */

5
src/target/stm8.h
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@ -11,11 +11,12 @@
struct target;
#define STM8_COMMON_MAGIC 0x53544D38
#define STM8_COMMON_MAGIC 0x53544D38U
#define STM8_NUM_CORE_REGS 6
struct stm8_common {
uint32_t common_magic;
unsigned int common_magic;
void *arch_info;
struct reg_cache *core_cache;
uint32_t core_regs[STM8_NUM_CORE_REGS];

5
src/target/x86_32_common.h
View File

@ -148,7 +148,7 @@ enum {
PMCR,
};
#define X86_32_COMMON_MAGIC 0x86328632
#define X86_32_COMMON_MAGIC 0x86328632U
enum {
/* memory read/write */
@ -200,7 +200,8 @@ struct swbp_mem_patch {
#define NUM_PM_REGS 18 /* regs used in save/restore */
struct x86_32_common {
uint32_t common_magic;
unsigned int common_magic;
void *arch_info;
enum x86_core_type core_type;
struct reg_cache *cache;

6
src/target/xscale.h
View File

@ -15,7 +15,7 @@
#include "armv4_5_mmu.h"
#include "trace.h"
#define XSCALE_COMMON_MAGIC 0x58534341
#define XSCALE_COMMON_MAGIC 0x58534341U
/* These four JTAG instructions are architecturally defined.
* Lengths are core-specific; originally 5 bits, later 7.
@ -71,11 +71,11 @@ struct xscale_trace {
};
struct xscale_common {
unsigned int common_magic;
/* armv4/5 common stuff */
struct arm arm;
int common_magic;
/* XScale registers (CP15, DBG) */
struct reg_cache *reg_cache;