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target: xscale make reset init work properly 

On XScale architecture, to write debug control register DCSR
and activate JTAG debug (ie. to choose Halt Mode), the
enabling can only be done while the board is held in reset
state (ie. PXAxx #RST line held low).

The current implementation writes to the register before
asserting the SRST line. Swap the order to activate the SRST
line before writing to DCSR.

Change-Id: I914b9d53d39bdeb5fe4ee5e11068cafafe0da4d2
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/1458
Tested-by: jenkins
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Robert Jarzmik 2013-06-24 04:52:51 +02:00 committed by Spencer Oliver
parent 12e25f34eb
commit 9188a9bc68
1 changed files with 7 additions and 7 deletions
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14
src/target/xscale.c
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@ -1447,6 +1447,13 @@ static int xscale_assert_reset(struct target *target)
LOG_DEBUG("target->state: %s",
target_state_name(target));
/* assert reset */
jtag_add_reset(0, 1);
/* sleep 1ms, to be sure we fulfill any requirements */
jtag_add_sleep(1000);
jtag_execute_queue();
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
@ -1463,13 +1470,6 @@ static int xscale_assert_reset(struct target *target)
xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
jtag_execute_queue();
/* assert reset */
jtag_add_reset(0, 1);
/* sleep 1ms, to be sure we fulfill any requirements */
jtag_add_sleep(1000);
jtag_execute_queue();
target->state = TARGET_RESET;
if (target->reset_halt) {