David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined: - ARMv5J "BXJ" (for Java/Jazelle) - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc) Compile-tested. This might not set up the simulator right for the ARMv6 single step support; only BXJ branches though, and docs to support Jazelle branching are non-public (still, sigh). ARMv6 instructions known to be mis-handled by this disassembler include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2 git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
ae17ce23eb
commit
997d5284cb
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@ -438,6 +438,323 @@ int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *in
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return ERROR_OK;
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}
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static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
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{
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unsigned rm = (opcode >> 0) & 0xf;
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unsigned rd = (opcode >> 12) & 0xf;
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unsigned rn = (opcode >> 16) & 0xf;
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char *type, *rot;
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switch ((opcode >> 24) & 0x3) {
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case 0:
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type = "B16";
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break;
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case 1:
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sprintf(cp, "UNDEFINED");
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return ARM_UNDEFINED_INSTRUCTION;
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case 2:
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type = "B";
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break;
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case 3:
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type = "H";
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break;
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}
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switch ((opcode >> 10) & 0x3) {
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case 0:
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rot = "";
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break;
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case 1:
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rot = ", ROR #8";
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break;
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case 2:
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rot = ", ROR #16";
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break;
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case 3:
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rot = ", ROR #24";
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break;
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}
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if (rn == 0xf) {
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sprintf(cp, "%cXT%s%s\tr%d, r%d%s",
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(opcode & (1 << 22)) ? 'U' : 'S',
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type, COND(opcode),
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rd, rm, rot);
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return ARM_MOV;
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} else {
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sprintf(cp, "%cXTA%s%s\tr%d, r%d, r%d%s",
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(opcode & (1 << 22)) ? 'U' : 'S',
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type, COND(opcode),
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rd, rn, rm, rot);
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return ARM_ADD;
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}
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}
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static int evaluate_p_add_sub(uint32_t opcode, uint32_t address, char *cp)
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{
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char *prefix;
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char *op;
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int type;
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switch ((opcode >> 20) & 0x7) {
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case 1:
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prefix = "S";
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break;
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case 2:
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prefix = "Q";
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break;
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case 3:
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prefix = "SH";
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break;
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case 5:
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prefix = "U";
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break;
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case 6:
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prefix = "UQ";
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break;
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case 7:
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prefix = "UH";
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break;
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default:
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goto undef;
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}
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switch ((opcode >> 5) & 0x7) {
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case 0:
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op = "ADD16";
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type = ARM_ADD;
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break;
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case 1:
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op = "ADDSUBX";
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type = ARM_ADD;
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break;
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case 2:
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op = "SUBADDX";
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type = ARM_SUB;
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break;
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case 3:
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op = "SUB16";
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type = ARM_SUB;
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break;
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case 4:
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op = "ADD8";
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type = ARM_ADD;
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break;
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case 7:
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op = "SUB8";
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type = ARM_SUB;
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break;
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default:
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goto undef;
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}
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sprintf(cp, "%s%s%s\tr%d, r%d, r%d", prefix, op, COND(opcode),
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(int) (opcode >> 12) & 0xf,
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf);
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return type;
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undef:
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/* these opcodes might be used someday */
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sprintf(cp, "UNDEFINED");
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return ARM_UNDEFINED_INSTRUCTION;
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}
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/* ARMv6 and later support "media" instructions (includes SIMD) */
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static int evaluate_media(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction)
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{
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char *cp = instruction->text;
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char *mnemonic = NULL;
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sprintf(cp,
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"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t",
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address, opcode);
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cp = strchr(cp, 0);
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/* parallel add/subtract */
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if ((opcode & 0x01800000) == 0x00000000) {
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instruction->type = evaluate_p_add_sub(opcode, address, cp);
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return ERROR_OK;
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}
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/* halfword pack */
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if ((opcode & 0x01f00020) == 0x00800000) {
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char *type, *shift;
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unsigned imm = (unsigned) (opcode >> 7) & 0x1f;
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if (opcode & (1 << 6)) {
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type = "TB";
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shift = "ASR";
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if (imm == 0)
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imm = 32;
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} else {
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type = "BT";
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shift = "LSL";
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}
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sprintf(cp, "PKH%s%s\tr%d, r%d, r%d, %s #%d",
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type, COND(opcode),
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(int) (opcode >> 12) & 0xf,
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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shift, imm);
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return ERROR_OK;
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}
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/* word saturate */
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if ((opcode & 0x01a00020) == 0x00a00000) {
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char *shift;
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unsigned imm = (unsigned) (opcode >> 7) & 0x1f;
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if (opcode & (1 << 6)) {
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shift = "ASR";
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if (imm == 0)
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imm = 32;
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} else {
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shift = "LSL";
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}
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sprintf(cp, "%cSAT%s\tr%d, #%d, r%d, %s #%d",
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(opcode & (1 << 22)) ? 'U' : 'S',
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COND(opcode),
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(int) (opcode >> 12) & 0xf,
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(int) (opcode >> 16) & 0x1f,
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(int) (opcode >> 0) & 0xf,
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shift, imm);
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return ERROR_OK;
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}
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/* sign extension */
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if ((opcode & 0x018000f0) == 0x00800070) {
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instruction->type = evaluate_extend(opcode, address, cp);
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return ERROR_OK;
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}
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/* multiplies */
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if ((opcode & 0x01f00080) == 0x01000000) {
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unsigned rn = (opcode >> 12) & 0xf;
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if (rn != 0xf)
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sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d",
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(opcode & (1 << 6)) ? 'S' : 'A',
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(opcode & (1 << 5)) ? "X" : "",
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COND(opcode),
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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(int) (opcode >> 8) & 0xf,
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rn);
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else
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sprintf(cp, "SMU%cD%s%s\tr%d, r%d, r%d",
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(opcode & (1 << 6)) ? 'S' : 'A',
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(opcode & (1 << 5)) ? "X" : "",
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COND(opcode),
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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(int) (opcode >> 8) & 0xf);
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return ERROR_OK;
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}
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if ((opcode & 0x01f00000) == 0x01400000) {
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sprintf(cp, "SML%cLD%s%s\tr%d, r%d, r%d, r%d",
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(opcode & (1 << 6)) ? 'S' : 'A',
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(opcode & (1 << 5)) ? "X" : "",
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COND(opcode),
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(int) (opcode >> 12) & 0xf,
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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(int) (opcode >> 8) & 0xf);
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return ERROR_OK;
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}
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if ((opcode & 0x01f00000) == 0x01500000) {
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unsigned rn = (opcode >> 12) & 0xf;
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switch (opcode & 0xc0) {
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case 3:
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if (rn == 0xf)
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goto undef;
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/* FALL THROUGH */
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case 0:
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break;
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default:
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goto undef;
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}
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if (rn != 0xf)
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sprintf(cp, "SMML%c%s%s\tr%d, r%d, r%d, r%d",
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(opcode & (1 << 6)) ? 'S' : 'A',
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(opcode & (1 << 5)) ? "R" : "",
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COND(opcode),
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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(int) (opcode >> 8) & 0xf,
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rn);
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else
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sprintf(cp, "SMMUL%s%s\tr%d, r%d, r%d",
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(opcode & (1 << 5)) ? "R" : "",
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COND(opcode),
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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(int) (opcode >> 8) & 0xf);
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return ERROR_OK;
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}
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/* simple matches against the remaining decode bits */
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switch (opcode & 0x01f000f0) {
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case 0x00a00030:
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case 0x00e00030:
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/* parallel halfword saturate */
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sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d",
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(opcode & (1 << 22)) ? 'U' : 'S',
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COND(opcode),
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(int) (opcode >> 12) & 0xf,
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf);
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return ERROR_OK;
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case 0x00b00030:
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mnemonic = "REV";
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break;
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case 0x00b000b0:
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mnemonic = "REV16";
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break;
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case 0x00f000b0:
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mnemonic = "REVSH";
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break;
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case 0x008000b0:
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/* select bytes */
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sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode),
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(int) (opcode >> 12) & 0xf,
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf);
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return ERROR_OK;
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case 0x01800010:
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/* unsigned sum of absolute differences */
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if (((opcode >> 12) & 0xf) == 0xf)
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sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode),
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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(int) (opcode >> 8) & 0xf);
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else
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sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode),
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(int) (opcode >> 16) & 0xf,
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(int) (opcode >> 0) & 0xf,
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(int) (opcode >> 8) & 0xf,
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(int) (opcode >> 12) & 0xf);
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return ERROR_OK;
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}
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if (mnemonic) {
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unsigned rm = (opcode >> 0) & 0xf;
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unsigned rd = (opcode >> 12) & 0xf;
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sprintf(cp, "%s%s\tr%d, r%d", mnemonic, COND(opcode), rm, rd);
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return ERROR_OK;
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}
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undef:
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/* these opcodes might be used someday */
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sprintf(cp, "UNDEFINED");
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return ERROR_OK;
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}
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/* Miscellaneous load/store instructions */
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int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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{
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@ -821,6 +1138,21 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
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instruction->info.b_bl_bx_blx.target_address = -1;
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}
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/* BXJ - "Jazelle" support (ARMv5-J) */
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if ((opcode & 0x006000f0) == 0x00200020)
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{
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uint8_t Rm;
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instruction->type = ARM_BX;
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Rm = opcode & 0xf;
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBXJ%s r%i",
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address, opcode, COND(opcode), Rm);
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instruction->info.b_bl_bx_blx.reg_operand = Rm;
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instruction->info.b_bl_bx_blx.target_address = -1;
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}
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/* CLZ */
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if ((opcode & 0x006000f0) == 0x00600010)
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{
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@ -1272,17 +1604,24 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *in
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/* catch opcodes with [27:25] = b011 */
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if ((opcode & 0x0e000000) == 0x06000000)
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{
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/* Undefined instruction */
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if ((opcode & 0x00000010) == 0x00000010)
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/* Load/store register offset */
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if ((opcode & 0x00000010) == 0x00000000)
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return evaluate_load_store(opcode, address, instruction);
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/* Architecturally Undefined instruction
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* ... don't expect these to ever be used
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*/
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if ((opcode & 0x07f000f0) == 0x07f000f0)
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{
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEF",
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address, opcode);
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return ERROR_OK;
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}
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/* Load/store register offset */
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return evaluate_load_store(opcode, address, instruction);
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/* "media" instructions */
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return evaluate_media(opcode, address, instruction);
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}
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/* catch opcodes with [27:25] = b100 */
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