From 9af662f95dff4346c95e9affef817c9234454aac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 10 May 2015 14:45:32 +0200 Subject: [PATCH] tcl/target: Add config for XMOS XS1-XAU8A-10's ARM core MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The XS1-XAU8A-10 has 8 xCORE cores and one ARM core. This config represents the ARM Cortex-M3 core, which is apparently Silicon Labs EFM32 Giant Gecko IP. Change-Id: I998360f096c759d2e274d96c1ca2e0450ba61146 Signed-off-by: Andreas Färber Reviewed-on: http://openocd.zylin.com/2762 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Spencer Oliver Reviewed-by: Paul Fertser --- tcl/target/xmos_xs1-xau8a-10_arm.cfg | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 tcl/target/xmos_xs1-xau8a-10_arm.cfg diff --git a/tcl/target/xmos_xs1-xau8a-10_arm.cfg b/tcl/target/xmos_xs1-xau8a-10_arm.cfg new file mode 100644 index 000000000..3fc197a3c --- /dev/null +++ b/tcl/target/xmos_xs1-xau8a-10_arm.cfg @@ -0,0 +1,16 @@ +# +# XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz +# +# http://www.xmos.com/products/silicon/xcore-xa/xa-series +# + +if { ![info exists CHIPNAME] } { + set CHIPNAME xcorexa +} + +if { ![info exists WORKAREASIZE] } { + # XS1-XAU8A-10-FB265: 128 KB SRAM + set WORKAREASIZE 0x20000 +} + +source [find target/efm32.cfg]