adiv6: add support for ROM tables in AP
ADIv6 adds AP that only contain a ROM table in the AP itself, that can point to other AP containing either another AP level ROM table or a MEM-AP to be parsed as usual. Add support for parsing AP level ROM tables. Change-Id: Ic25863b16463b8a6adc3b15e26db7fdca858d6df Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6467 Tested-by: jenkins
This commit is contained in:
Antonio Borneo
parent
b987a419b4
commit
9f0ac0e6bb
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@ -928,6 +928,7 @@ static const struct {
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};
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#define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
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#define DEVARCH_MEM_AP ARCH_ID(ARM_ID, 0x0A17)
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#define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
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static const char *class0x9_devarch_description(uint32_t devarch)
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@ -1180,6 +1181,17 @@ int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap
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return ERROR_OK;
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}
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/**
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* Method to access the CoreSight component.
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* On ADIv5, CoreSight components are on the bus behind a MEM-AP.
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* On ADIv6, CoreSight components can either be on the bus behind a MEM-AP
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* or directly in the AP.
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*/
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enum coresight_access_mode {
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CS_ACCESS_AP,
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CS_ACCESS_MEM_AP,
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};
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/** Holds registers and coordinates of a CoreSight component */
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struct cs_component_vals {
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struct adiv5_ap *ap;
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@ -1189,19 +1201,43 @@ struct cs_component_vals {
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uint32_t devarch;
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uint32_t devid;
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uint32_t devtype_memtype;
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enum coresight_access_mode mode;
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};
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/**
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* Helper to read CoreSight component's registers, either on the bus
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* behind a MEM-AP or directly in the AP.
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*
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* @param mode Method to access the component (AP or MEM-AP).
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* @param ap Pointer to AP containing the component.
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* @param component_base On MEM-AP access method, base address of the component.
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* @param reg Offset of the component's register to read.
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* @param value Pointer to the store the read value.
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*
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* @return ERROR_OK on success, else a fault code.
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*/
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static int dap_queue_read_reg(enum coresight_access_mode mode, struct adiv5_ap *ap,
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uint64_t component_base, unsigned int reg, uint32_t *value)
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{
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if (mode == CS_ACCESS_AP)
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return dap_queue_ap_read(ap, reg, value);
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/* mode == CS_ACCESS_MEM_AP */
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return mem_ap_read_u32(ap, component_base + reg, value);
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}
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/**
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* Read the CoreSight registers needed during ROM Table Parsing (RTP).
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*
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* @param mode Method to access the component (AP or MEM-AP).
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* @param ap Pointer to AP containing the component.
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* @param component_base On MEM-AP access method, base address of the component.
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* @param v Pointer to the struct holding the value of registers.
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*
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* @return ERROR_OK on success, else a fault code.
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*/
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static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
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struct cs_component_vals *v)
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static int rtp_read_cs_regs(enum coresight_access_mode mode, struct adiv5_ap *ap,
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target_addr_t component_base, struct cs_component_vals *v)
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{
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assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
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assert(ap && v);
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@ -1212,6 +1248,7 @@ static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
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v->ap = ap;
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v->component_base = component_base;
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v->mode = mode;
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/* sort by offset to gain speed */
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@ -1221,35 +1258,35 @@ static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
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* without triggering error. Read them for eventual use on Class 0x9.
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*/
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVARCH, &v->devarch);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVARCH, &v->devarch);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVID, &v->devid);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVID, &v->devid);
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/* Same address as ARM_CS_C1_MEMTYPE */
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR4, &pid4);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR0, &pid0);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR1, &pid1);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR2, &pid2);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR3, &pid3);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR0, &cid0);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR1, &cid1);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR2, &cid2);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
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retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR3, &cid3);
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if (retval == ERROR_OK)
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retval = dap_run(ap->dap);
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@ -1572,6 +1609,14 @@ static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
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* Actions/operations to be executed while parsing ROM tables.
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*/
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struct rtp_ops {
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/**
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* Executed at the start of a new AP, typically to print the AP header.
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* @param ap Pointer to AP.
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* @param depth The current depth level of ROM table.
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* @param priv Pointer to private data.
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* @return ERROR_OK on success, else a fault code.
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*/
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int (*ap_header)(struct adiv5_ap *ap, int depth, void *priv);
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/**
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* Executed at the start of a new MEM-AP, typically to print the MEM-AP header.
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* @param retval Error encountered while reading AP.
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@ -1612,6 +1657,18 @@ struct rtp_ops {
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void *priv;
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};
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/**
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* Wrapper around struct rtp_ops::ap_header.
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*/
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static int rtp_ops_ap_header(const struct rtp_ops *ops,
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struct adiv5_ap *ap, int depth)
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{
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if (ops->ap_header)
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return ops->ap_header(ap, depth, ops->priv);
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return ERROR_OK;
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}
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/**
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* Wrapper around struct rtp_ops::mem_ap_header.
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* Input parameter @a retval is propagated.
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@ -1671,13 +1728,18 @@ static int rtp_ops_rom_table_entry(const struct rtp_ops *ops,
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*/
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#define CORESIGHT_COMPONENT_FOUND (1)
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static int rtp_cs_component(const struct rtp_ops *ops,
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struct adiv5_ap *ap, target_addr_t dbgbase, int depth);
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static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth);
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static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_ops *ops,
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struct adiv5_ap *ap, target_addr_t dbgbase, bool *is_mem_ap, int depth);
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static int rtp_rom_loop(const struct rtp_ops *ops,
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static int rtp_rom_loop(enum coresight_access_mode mode, const struct rtp_ops *ops,
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struct adiv5_ap *ap, target_addr_t base_address, int depth,
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unsigned int width, unsigned int max_entries)
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{
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/* ADIv6 AP ROM table provide offset from current AP */
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if (mode == CS_ACCESS_AP)
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base_address = ap->ap_num;
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assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
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unsigned int offset = 0;
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@ -1687,10 +1749,10 @@ static int rtp_rom_loop(const struct rtp_ops *ops,
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target_addr_t component_base;
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unsigned int saved_offset = offset;
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int retval = mem_ap_read_u32(ap, base_address + offset, &romentry_low);
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int retval = dap_queue_read_reg(mode, ap, base_address, offset, &romentry_low);
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offset += 4;
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if (retval == ERROR_OK && width == 64) {
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retval = mem_ap_read_u32(ap, base_address + offset, &romentry_high);
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retval = dap_queue_read_reg(mode, ap, base_address, offset, &romentry_high);
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offset += 4;
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}
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if (retval == ERROR_OK)
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@ -1724,7 +1786,18 @@ static int rtp_rom_loop(const struct rtp_ops *ops,
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continue;
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/* Recurse */
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retval = rtp_cs_component(ops, ap, component_base, depth + 1);
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if (mode == CS_ACCESS_AP) {
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struct adiv5_ap *next_ap = dap_get_ap(ap->dap, component_base);
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if (!next_ap) {
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LOG_DEBUG("Wrong AP # 0x%" PRIx64, component_base);
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continue;
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}
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retval = rtp_ap(ops, next_ap, depth + 1);
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dap_put_ap(next_ap);
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} else {
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/* mode == CS_ACCESS_MEM_AP */
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retval = rtp_cs_component(mode, ops, ap, component_base, NULL, depth + 1);
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}
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if (retval == CORESIGHT_COMPONENT_FOUND)
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return CORESIGHT_COMPONENT_FOUND;
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if (retval != ERROR_OK) {
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@ -1737,18 +1810,21 @@ static int rtp_rom_loop(const struct rtp_ops *ops,
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return ERROR_OK;
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}
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static int rtp_cs_component(const struct rtp_ops *ops,
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struct adiv5_ap *ap, target_addr_t base_address, int depth)
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static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_ops *ops,
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struct adiv5_ap *ap, target_addr_t base_address, bool *is_mem_ap, int depth)
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{
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struct cs_component_vals v;
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int retval;
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assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
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if (is_mem_ap)
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*is_mem_ap = false;
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if (depth > ROM_TABLE_MAX_DEPTH)
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retval = ERROR_FAIL;
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else
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retval = rtp_read_cs_regs(ap, base_address, &v);
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retval = rtp_read_cs_regs(mode, ap, base_address, &v);
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retval = rtp_ops_cs_component(ops, retval, &v, depth);
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if (retval == CORESIGHT_COMPONENT_FOUND)
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@ -1762,20 +1838,23 @@ static int rtp_cs_component(const struct rtp_ops *ops,
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const unsigned int class = ARM_CS_CIDR_CLASS(v.cid);
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if (class == ARM_CS_CLASS_0X1_ROM_TABLE)
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return rtp_rom_loop(ops, ap, base_address, depth, 32, 960);
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return rtp_rom_loop(mode, ops, ap, base_address, depth, 32, 960);
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if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
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if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
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return ERROR_OK;
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if (is_mem_ap && (v.devarch & DEVARCH_ID_MASK) == DEVARCH_MEM_AP)
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*is_mem_ap = true;
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/* quit if not ROM table */
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if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
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return ERROR_OK;
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if ((v.devid & ARM_CS_C9_DEVID_FORMAT_MASK) == ARM_CS_C9_DEVID_FORMAT_64BIT)
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return rtp_rom_loop(ops, ap, base_address, depth, 64, 256);
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return rtp_rom_loop(mode, ops, ap, base_address, depth, 64, 256);
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else
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return rtp_rom_loop(ops, ap, base_address, depth, 32, 512);
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return rtp_rom_loop(mode, ops, ap, base_address, depth, 32, 512);
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}
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/* Class other than 0x1 and 0x9 */
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@ -1784,10 +1863,26 @@ static int rtp_cs_component(const struct rtp_ops *ops,
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static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
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{
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int retval;
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uint32_t apid;
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target_addr_t dbgbase, invalid_entry;
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int retval = rtp_ops_ap_header(ops, ap, depth);
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if (retval != ERROR_OK || depth > ROM_TABLE_MAX_DEPTH)
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return ERROR_OK; /* Don't abort recursion */
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if (is_adiv6(ap->dap)) {
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bool is_mem_ap;
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retval = rtp_cs_component(CS_ACCESS_AP, ops, ap, 0, &is_mem_ap, depth);
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if (retval == CORESIGHT_COMPONENT_FOUND)
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return CORESIGHT_COMPONENT_FOUND;
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if (retval != ERROR_OK)
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return ERROR_OK; /* Don't abort recursion */
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if (!is_mem_ap)
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return ERROR_OK;
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/* Continue for an ADIv6 MEM-AP */
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}
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/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
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retval = dap_get_debugbase(ap, &dbgbase, &apid);
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if (retval != ERROR_OK)
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@ -1811,7 +1906,8 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
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invalid_entry = 0xFFFFFFFFul;
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if (dbgbase != invalid_entry && (dbgbase & 0x3) != 0x2) {
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retval = rtp_cs_component(ops, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, depth);
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retval = rtp_cs_component(CS_ACCESS_MEM_AP, ops, ap,
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dbgbase & 0xFFFFFFFFFFFFF000ull, NULL, depth);
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if (retval == CORESIGHT_COMPONENT_FOUND)
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return CORESIGHT_COMPONENT_FOUND;
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}
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@ -1822,6 +1918,19 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
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/* Actions for command "dap info" */
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static int dap_info_ap_header(struct adiv5_ap *ap, int depth, void *priv)
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{
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struct command_invocation *cmd = priv;
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if (depth > ROM_TABLE_MAX_DEPTH) {
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command_print(cmd, "\tTables too deep");
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return ERROR_FAIL;
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}
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command_print(cmd, "%sAP # 0x%" PRIx64, (depth) ? "\t\t" : "", ap->ap_num);
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return ERROR_OK;
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}
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static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
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target_addr_t dbgbase, uint32_t apid, int depth, void *priv)
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{
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@ -1842,8 +1951,6 @@ static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
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if (depth)
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snprintf(tabs, sizeof(tabs), "\t[L%02d] ", depth);
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command_print(cmd, "%sAP # 0x%" PRIx64, tabs, ap->ap_num);
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command_print(cmd, "\t\tAP ID register 0x%8.8" PRIx32, apid);
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if (apid == 0) {
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command_print(cmd, "\t\tNo AP found at this AP#0x%" PRIx64, ap->ap_num);
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@ -1887,7 +1994,8 @@ static int dap_info_cs_component(int retval, struct cs_component_vals *v, int de
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return ERROR_FAIL;
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}
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command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
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if (v->mode == CS_ACCESS_MEM_AP)
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command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
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if (retval != ERROR_OK) {
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command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
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@ -1998,6 +2106,7 @@ static int dap_info_rom_table_entry(int retval, int depth,
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int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
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{
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struct rtp_ops dap_info_ops = {
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.ap_header = dap_info_ap_header,
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.mem_ap_header = dap_info_mem_ap_header,
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.cs_component = dap_info_cs_component,
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.rom_table_entry = dap_info_rom_table_entry,
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@ -2054,6 +2163,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type,
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.idx = core_id,
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};
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struct rtp_ops dap_lookup_cs_component_ops = {
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.ap_header = NULL,
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.mem_ap_header = NULL,
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.cs_component = dap_lookup_cs_component_cs_component,
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.rom_table_entry = NULL,
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