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aarch64: discard async aborts on entering debug state

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recommended for Corte-A8 cores, not sure if necessary
for ARMv8 based cores as well.

Change-Id: Ibcb36170c5fac6a6b132de17f734c70a56919f9b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky 2016-10-20 16:23:40 +02:00
parent 0a53bae0ea
commit 9f4b5b509f
4 changed files with 17 additions and 2 deletions
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7
src/target/aarch64.c
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@ -663,11 +663,16 @@ static int aarch64_debug_entry(struct target *target)
/* make sure to clear all sticky errors */
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
/* discard async exceptions */
if (retval == ERROR_OK)
retval = dpm->instr_cpsr_sync(dpm);
if (retval != ERROR_OK)
return retval;
/* Examine debug reason */
armv8_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
armv8_dpm_report_dscr(dpm, aarch64->cpudbg_dscr);
/* save address of instruction that triggered the watchpoint? */
if (target->debug_reason == DBG_REASON_WATCHPOINT) {

7
src/target/armv8_dpm.c
View File

@ -360,9 +360,14 @@ static int dpmv8_instr_write_data_r0_64(struct arm_dpm *dpm,
static int dpmv8_instr_cpsr_sync(struct arm_dpm *dpm)
{
int retval;
struct armv8_common *armv8 = dpm->arm->arch_info;
/* "Prefetch flush" after modifying execution status in CPSR */
return dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_DSB_SY), NULL);
retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_DSB_SY), &dpm->dscr);
if (retval == ERROR_OK)
dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_ISB_SY), &dpm->dscr);
return retval;
}
static int dpmv8_instr_read_data_dcc(struct arm_dpm *dpm,

2
src/target/armv8_opcodes.c
View File

@ -37,6 +37,7 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DSB_SY] = ARMV8_DSB_SY,
[ARMV8_OPC_DCPS] = ARMV8_DCPS(0, 11),
[ARMV8_OPC_DRPS] = ARMV8_DRPS,
[ARMV8_OPC_ISB_SY] = ARMV8_ISB,
};
static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
@ -53,6 +54,7 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DSB_SY] = ARMV8_DSB_SY_T1,
[ARMV8_OPC_DCPS] = ARMV8_DCPS_T1(0),
[ARMV8_OPC_DRPS] = ARMV8_ERET_T1,
[ARMV8_OPC_ISB_SY] = ARMV8_ISB_SY_T1,
};
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)

3
src/target/armv8_opcodes.h
View File

@ -135,6 +135,8 @@
#define ARMV8_DSB_SY 0xd5033F9F
#define ARMV8_DSB_SY_T1 0xf3bf8f4f
#define ARMV8_ISB 0xd5033fdf
#define ARMV8_ISB_SY_T1 0xf3bf8f6f
#define ARMV8_MRS(System, Rt) (0xd5300000 | ((System) << 5) | (Rt))
/* ARM V8 Move to system register. */
@ -173,6 +175,7 @@ enum armv8_opcode {
ARMV8_OPC_DSB_SY,
ARMV8_OPC_DCPS,
ARMV8_OPC_DRPS,
ARMV8_OPC_ISB_SY,
ARMV8_OPC_NUM,
};