David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register handling ... don't use parallel
arrays (error prone) or assume all registers are 32-bits wide (they can have fewer bits); don't use spaces in register names, so they can be passed more easily to the "reg" command. Minor updates for ARM9 vector_catch support: it's an 8-bit value. This seems to help this core's vector_catch command work a bit better; but its behavior wih the register cache is still goofy. git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
5badd9b29a
commit
a4c7e2dd96
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@ -995,7 +995,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha
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embeddedice_read_reg(vector_catch);
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/* get the current setting */
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vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
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vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
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if (argc > 0)
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{
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@ -1028,7 +1028,9 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha
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command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
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/* reread current setting */
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vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
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vector_catch_value = buf_get_u32(
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vector_catch->value,
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0, 8);
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break;
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}
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@ -1036,7 +1038,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha
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}
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/* store new settings */
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buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
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buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
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embeddedice_store_reg(vector_catch);
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}
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@ -29,6 +29,7 @@
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#include "embeddedice.h"
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#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
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#if 0
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static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
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@ -40,38 +41,102 @@ static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
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};
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#endif
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static int embeddedice_reg_arch_info[] =
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{
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0x0, 0x1, 0x4, 0x5,
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0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
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0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
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0x2
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/*
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* From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
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*/
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static const struct {
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char *name;
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unsigned short addr;
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unsigned short width;
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} eice_regs[] = {
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[EICE_DBG_CTRL] = {
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.name = "debug_ctrl",
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.addr = 0,
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/* width is assigned based on EICE version */
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},
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[EICE_DBG_STAT] = {
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.name = "debug_status",
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.addr = 1,
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/* width is assigned based on EICE version */
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},
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[EICE_COMMS_CTRL] = {
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.name = "comms_ctrl",
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.addr = 4,
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.width = 6,
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},
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[EICE_COMMS_DATA] = {
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.name = "comms_data",
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.addr = 5,
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.width = 32,
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},
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[EICE_W0_ADDR_VALUE] = {
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.name = "watch_0_addr_value",
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.addr = 8,
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.width = 32,
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},
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[EICE_W0_ADDR_MASK] = {
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.name = "watch_0_addr_mask",
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.addr = 9,
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.width = 32,
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},
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[EICE_W0_DATA_VALUE ] = {
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.name = "watch_0_data_value",
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.addr = 10,
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.width = 32,
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},
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[EICE_W0_DATA_MASK] = {
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.name = "watch_0_data_mask",
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.addr = 11,
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.width = 32,
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},
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[EICE_W0_CONTROL_VALUE] = {
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.name = "watch_0_control_value",
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.addr = 12,
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.width = 9,
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},
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[EICE_W0_CONTROL_MASK] = {
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.name = "watch_0_control_mask",
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.addr = 13,
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.width = 8,
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},
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[EICE_W1_ADDR_VALUE] = {
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.name = "watch_1_addr_value",
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.addr = 16,
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.width = 32,
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},
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[EICE_W1_ADDR_MASK] = {
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.name = "watch_1_addr_mask",
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.addr = 17,
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.width = 32,
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},
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[EICE_W1_DATA_VALUE] = {
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.name = "watch_1_data_value",
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.addr = 18,
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.width = 32,
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},
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[EICE_W1_DATA_MASK] = {
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.name = "watch_1_data_mask",
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.addr = 19,
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.width = 32,
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},
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[EICE_W1_CONTROL_VALUE] = {
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.name = "watch_1_control_value",
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.addr = 20,
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.width = 9,
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},
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[EICE_W1_CONTROL_MASK] = {
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.name = "watch_1_control_mask",
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.addr = 21,
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.width = 8,
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},
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/* vector_catch isn't always present */
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[EICE_VEC_CATCH] = {
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.name = "vector_catch",
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.addr = 2,
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.width = 8,
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},
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};
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static char* embeddedice_reg_list[] =
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{
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"debug_ctrl",
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"debug_status",
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"comms_ctrl",
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"comms_data",
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"watch 0 addr value",
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"watch 0 addr mask",
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"watch 0 data value",
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"watch 0 data mask",
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"watch 0 control value",
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"watch 0 control mask",
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"watch 1 addr value",
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"watch 1 addr mask",
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"watch 1 data value",
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"watch 1 data mask",
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"watch 1 control value",
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"watch 1 control mask",
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"vector catch"
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};
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static int embeddedice_reg_arch_type = -1;
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@ -84,18 +149,18 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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reg_t *reg_list = NULL;
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embeddedice_reg_t *arch_info = NULL;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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int num_regs;
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int num_regs = ARRAY_SIZE(eice_regs);
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int i;
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int eice_version = 0;
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/* register a register arch-type for EmbeddedICE registers only once */
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if (embeddedice_reg_arch_type == -1)
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embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
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embeddedice_reg_arch_type = register_reg_arch_type(
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embeddedice_get_reg, embeddedice_set_reg_w_exec);
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if (arm7_9->has_vector_catch)
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num_regs = 17;
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else
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num_regs = 16;
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/* vector_catch isn't always present */
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if (!arm7_9->has_vector_catch)
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num_regs--;
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/* the actual registers are kept in two arrays */
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reg_list = calloc(num_regs, sizeof(reg_t));
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@ -110,8 +175,8 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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/* set up registers */
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for (i = 0; i < num_regs; i++)
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{
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reg_list[i].name = embeddedice_reg_list[i];
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reg_list[i].size = 32;
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reg_list[i].name = eice_regs[i].name;
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reg_list[i].size = eice_regs[i].width;
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].bitfield_desc = NULL;
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@ -119,7 +184,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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reg_list[i].value = calloc(1, 4);
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reg_list[i].arch_info = &arch_info[i];
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reg_list[i].arch_type = embeddedice_reg_arch_type;
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arch_info[i].addr = embeddedice_reg_arch_info[i];
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arch_info[i].addr = eice_regs[i].addr;
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arch_info[i].jtag_info = jtag_info;
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}
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@ -137,43 +202,57 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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}
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eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
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LOG_DEBUG("Embedded ICE version %d", eice_version);
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switch (eice_version)
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{
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case 1:
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/* ARM7TDMI r3, ARM7TDMI-S r3
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*
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* REVISIT docs say ARM7TDMI-S r4 uses version 1 but
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* that it has 6-bit CTRL and 5-bit STAT... doc bug?
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* ARM7TDMI r4 docs say EICE v4.
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*/
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reg_list[EICE_DBG_CTRL].size = 3;
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reg_list[EICE_DBG_STAT].size = 5;
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break;
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case 2:
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/* ARM9TDMI */
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reg_list[EICE_DBG_CTRL].size = 4;
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reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_single_step = 1;
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break;
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case 3:
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LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
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LOG_ERROR("EmbeddedICE v%d handling might be broken",
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eice_version);
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reg_list[EICE_DBG_CTRL].size = 6;
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reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_single_step = 1;
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arm7_9->has_monitor_mode = 1;
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break;
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case 4:
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/* ARM7TDMI r4 */
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reg_list[EICE_DBG_CTRL].size = 6;
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reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_monitor_mode = 1;
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break;
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case 5:
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/* ARM9E-S rev 1 */
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reg_list[EICE_DBG_CTRL].size = 6;
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reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_single_step = 1;
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arm7_9->has_monitor_mode = 1;
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break;
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case 6:
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/* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
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reg_list[EICE_DBG_CTRL].size = 6;
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reg_list[EICE_DBG_STAT].size = 10;
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/* DBG_STAT has MOE bits */
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arm7_9->has_monitor_mode = 1;
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break;
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case 7:
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LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
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LOG_ERROR("EmbeddedICE v%d handling might be broken",
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eice_version);
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reg_list[EICE_DBG_CTRL].size = 6;
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reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_monitor_mode = 1;
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@ -276,7 +355,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* chec
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* EICE_COMMS_DATA would read the register twice
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* reading the control register is safe
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*/
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buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
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buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr);
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jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
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@ -305,7 +384,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
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fields[1].tap = jtag_info->tap;
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fields[1].num_bits = 5;
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fields[1].out_value = field1_out;
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buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
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buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
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fields[1].in_value = NULL;
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fields[2].tap = jtag_info->tap;
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@ -322,7 +401,8 @@ int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
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* to avoid reading additional data from the DCC data reg
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*/
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if (size == 1)
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buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
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buf_set_u32(fields[1].out_value, 0, 5,
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eice_regs[EICE_COMMS_CTRL].addr);
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fields[0].in_value = (uint8_t *)data;
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jtag_add_dr_scan(3, fields, jtag_get_end_state());
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@ -407,7 +487,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
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fields[1].tap = jtag_info->tap;
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fields[1].num_bits = 5;
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fields[1].out_value = field1_out;
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buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
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buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
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fields[1].in_value = NULL;
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fields[2].tap = jtag_info->tap;
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@ -462,7 +542,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout)
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fields[1].tap = jtag_info->tap;
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fields[1].num_bits = 5;
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fields[1].out_value = field1_out;
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buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
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buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
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fields[1].in_value = NULL;
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fields[2].tap = jtag_info->tap;
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