David Brownell <david-b@pacbell.net> Clock updates/fixes for the Stellaris flash driver:
- Bugfixes:
* internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
+ except new Tempest parts where it's 16 MHz (and calibrated!)
+ or some old Sandstorm ones, where 15 MHz was valid
* crystal config:
+ read and use the crystal config, don't assume 6 MHz
+ know when that field is 4 bits vs 5
* an RCC2 register may be overriding the original RCC
+ more clock source options
+ bigger dividers
+ fractional dividers on Tempest (NYET handled)
* there's a 30 KHz osc on newer chips (for deep sleep)
* there's a 32768 Hz osc on newer chips (for hibernation)
- Cosmetic
* say "rev A0" not "vA.0", to match vendor docs
* don't always report master clock as an "estimate":
+ give the error bound if it's approximate, like "±30%"
+ else don't say anything
* fix whitespace and caps in some messages
* these are not AT91SAM chips!!
Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.
That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor. What's less clear is which chips are "old" like that.
Lightly tested, on a DustDevil part.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
34e8c67b1f
commit
a5354ff5cb
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@ -257,7 +257,10 @@ static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char
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/* part wasn't probed for info yet */
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stellaris_info->did1 = 0;
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/* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
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/* TODO Specify the main crystal speed in kHz using an optional
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* argument; ditto, the speed of an external oscillator used
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* instead of a crystal. Avoid programming flash using IOSC.
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*/
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return ERROR_OK;
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}
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@ -294,7 +297,8 @@ static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
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}
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printed = snprintf(buf,
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buf_size,
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"\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
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"\nTI/LMI Stellaris information: Chip is "
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"class %i (%s) %s rev %c%i\n",
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device_class,
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StellarisClassname[device_class],
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stellaris_info->target_name,
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@ -305,10 +309,11 @@ static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
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printed = snprintf(buf,
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buf_size,
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"did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32 ", eproc: %s, ramsize:%ik, flashsize: %ik\n",
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"did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
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", eproc: %s, ramsize: %ik, flashsize: %ik\n",
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stellaris_info->did1,
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stellaris_info->did1,
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"ARMV7M",
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"ARMv7M",
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(int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
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(int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
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buf += printed;
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@ -316,9 +321,12 @@ static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
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printed = snprintf(buf,
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buf_size,
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"master clock(estimated): %ikHz, rcc is 0x%" PRIx32 " \n",
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"master clock: %ikHz%s, "
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"rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
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(int)(stellaris_info->mck_freq / 1000),
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stellaris_info->rcc);
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stellaris_info->mck_desc,
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stellaris_info->rcc,
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stellaris_info->rcc2);
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buf += printed;
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buf_size -= printed;
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@ -353,38 +361,103 @@ static uint32_t stellaris_get_flash_status(flash_bank_t *bank)
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/** Read clock configuration and set stellaris_info->usec_clocks*/
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static const unsigned rcc_xtal[32] = {
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[0x00] = 1000000, /* no pll */
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[0x01] = 1843200, /* no pll */
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[0x02] = 2000000, /* no pll */
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[0x03] = 2457600, /* no pll */
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[0x04] = 3579545,
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[0x05] = 3686400,
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[0x06] = 4000000, /* usb */
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[0x07] = 4096000,
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[0x08] = 4915200,
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[0x09] = 5000000, /* usb */
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[0x0a] = 5120000,
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[0x0b] = 6000000, /* (reset) usb */
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[0x0c] = 6144000,
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[0x0d] = 7372800,
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[0x0e] = 8000000, /* usb */
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[0x0f] = 8192000,
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/* parts before DustDevil use just 4 bits for xtal spec */
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[0x10] = 10000000, /* usb */
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[0x11] = 12000000, /* usb */
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[0x12] = 12288000,
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[0x13] = 13560000,
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[0x14] = 14318180,
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[0x15] = 16000000, /* usb */
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[0x16] = 16384000,
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};
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static void stellaris_read_clock_info(flash_bank_t *bank)
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{
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stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
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target_t *target = bank->target;
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uint32_t rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
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uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
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unsigned xtal;
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unsigned long mainfreq;
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target_read_u32(target, SCB_BASE | RCC, &rcc);
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LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
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target_read_u32(target, SCB_BASE | RCC2, &rcc2);
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LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
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target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
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LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
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stellaris_info->rcc = rcc;
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stellaris_info->rcc = rcc2;
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sysdiv = (rcc >> 23) & 0xF;
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usesysdiv = (rcc >> 22) & 0x1;
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bypass = (rcc >> 11) & 0x1;
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oscsrc = (rcc >> 4) & 0x3;
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/* xtal = (rcc >> 6)&0xF; */
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xtal = (rcc >> 6) & stellaris_info->xtal_mask;
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/* NOTE: post-Sandstorm parts have RCC2 which may override
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* parts of RCC ... with more sysdiv options, option for
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* 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
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* as zero, so the "use RCC2" flag is always clear.
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*/
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if (rcc2 & (1 << 31)) {
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sysdiv = (rcc2 >> 23) & 0x3F;
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bypass = (rcc2 >> 11) & 0x1;
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oscsrc = (rcc2 >> 4) & 0x7;
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/* FIXME Tempest parts have an additional lsb for
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* fractional sysdiv (200 MHz / 2.5 == 80 MHz)
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*/
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}
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stellaris_info->mck_desc = "";
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switch (oscsrc)
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{
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case 0:
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mainfreq = 6000000; /* Default xtal */
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case 0: /* MOSC */
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mainfreq = rcc_xtal[xtal];
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break;
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case 1:
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mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */
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case 1: /* IOSC */
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mainfreq = stellaris_info->iosc_freq;
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stellaris_info->mck_desc = stellaris_info->iosc_desc;
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break;
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case 2:
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mainfreq = 5625000; /* Internal osc. / 4 */
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case 2: /* IOSC/4 */
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mainfreq = stellaris_info->iosc_freq / 4;
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stellaris_info->mck_desc = stellaris_info->iosc_desc;
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break;
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case 3:
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LOG_WARNING("Invalid oscsrc (3) in rcc register");
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mainfreq = 6000000;
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case 3: /* lowspeed */
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/* Sandstorm doesn't have this 30K +/- 30% osc */
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mainfreq = 30000;
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stellaris_info->mck_desc = " (±30%)";
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break;
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case 8: /* hibernation osc */
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/* not all parts support hibernation */
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mainfreq = 32768;
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break;
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default: /* NOTREACHED */
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@ -392,8 +465,11 @@ static void stellaris_read_clock_info(flash_bank_t *bank)
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break;
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}
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/* PLL is used if it's not bypassed; its output is 200 MHz
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* even when it runs at 400 MHz (adds divide-by-two stage).
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*/
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if (!bypass)
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mainfreq = 200000000; /* PLL out frec */
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mainfreq = 200000000;
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if (usesysdiv)
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stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
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@ -487,6 +563,48 @@ static int stellaris_read_part_info(struct flash_bank_s *bank)
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LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
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}
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/* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
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* is 12 MHz, but some older parts have 15 MHz. A few data sheets
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* even give _both_ numbers! We'll use current numbers; IOSC is
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* always approximate.
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*
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* For Tempest: IOSC is calibrated, 16 MHz
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*/
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stellaris_info->iosc_freq = 12000000;
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stellaris_info->iosc_desc = " (±30%)";
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stellaris_info->xtal_mask = 0x0f;
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switch ((did0 >> 28) & 0x7) {
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case 0: /* Sandstorm */
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/*
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* Current (2009-August) parts seem to be rev C2 and use 12 MHz.
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* Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
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* (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
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*/
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if (((did0 >> 16) & 0xff) <= 2) {
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stellaris_info->iosc_freq = 15000000;
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stellaris_info->iosc_desc = " (±50%)";
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}
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break;
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case 1:
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switch ((did0 >> 16) & 0xff) {
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case 1: /* Fury */
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break;
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case 4: /* Tempest */
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stellaris_info->iosc_freq = 16000000; /* +/- 1% */
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stellaris_info->iosc_desc = " (±1%)";
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/* FALL THROUGH */
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case 3: /* DustDevil */
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stellaris_info->xtal_mask = 0x1f;
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break;
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default:
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LOG_WARNING("Unknown did0 class");
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}
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default:
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break;
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LOG_WARNING("Unknown did0 version");
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}
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for (i = 0; StellarisParts[i].partno; i++)
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{
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if (StellarisParts[i].partno == ((did1 >> 16) & 0xFF))
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@ -547,7 +665,7 @@ static int stellaris_protect_check(struct flash_bank_s *bank)
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if (stellaris_info->did1 == 0)
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{
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LOG_WARNING("Cannot identify target as an AT91SAM");
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LOG_WARNING("Cannot identify target as Stellaris");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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@ -45,8 +45,13 @@ typedef struct stellaris_flash_bank_s
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/* main clock status */
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uint32_t rcc;
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uint32_t rcc2;
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uint8_t mck_valid;
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uint8_t xtal_mask;
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uint32_t iosc_freq;
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uint32_t mck_freq;
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const char *iosc_desc;
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const char *mck_desc;
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} stellaris_flash_bank_t;
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/* STELLARIS control registers */
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@ -62,6 +67,7 @@ typedef struct stellaris_flash_bank_s
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#define RIS 0x050
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#define RCC 0x060
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#define PLLCFG 0x064
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#define RCC2 0x070
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#define FMPRE 0x130
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#define FMPPE 0x134
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