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adiv6: re-organize mem_ap registers definition 

ADIv5 MEM-AP registers are a subset of ADIv6 MEM-AP registers and
are located at different offset.

To prepare for introducing ADIv6, add 'struct adiv5_dap *' as
argument to ADIv5 registers macro.
Check the ADI version and use the proper address.
Both adapter drivers rshim and stlink are ADIv5 only, so let them
use the ADIv5 macros only.

Split from change https://review.openocd.org/6077/

Change-Id: Ib861ddcdab74637b2082cc9f2612dea0007d77b1
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6457
Tested-by: jenkins
This commit is contained in:
Kevin Burke 2021-08-21 19:12:01 +02:00 committed by Antonio Borneo
parent 1fe82f9f1d
commit a6e4aabc66
5 changed files with 143 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/jtag/drivers/rshim.c
View File

@ -283,35 +283,35 @@ static int rshim_ap_q_read(struct adiv5_ap *ap, unsigned int reg,
int rc = ERROR_OK, tile;
switch (reg) {
case MEM_AP_REG_CSW:
case ADIV5_MEM_AP_REG_CSW:
*data = ap_csw;
break;
case MEM_AP_REG_CFG:
case ADIV5_MEM_AP_REG_CFG:
*data = 0;
break;
case MEM_AP_REG_BASE:
case ADIV5_MEM_AP_REG_BASE:
*data = RSH_CS_ROM_BASE;
break;
case AP_REG_IDR:
case ADIV5_AP_REG_IDR:
if (ap->ap_num == 0)
*data = APB_AP_IDR;
else
*data = 0;
break;
case MEM_AP_REG_BD0:
case MEM_AP_REG_BD1:
case MEM_AP_REG_BD2:
case MEM_AP_REG_BD3:
case ADIV5_MEM_AP_REG_BD0:
case ADIV5_MEM_AP_REG_BD1:
case ADIV5_MEM_AP_REG_BD2:
case ADIV5_MEM_AP_REG_BD3:
addr = (ap_tar & ~0xf) + (reg & 0x0C);
ap_addr_2_tile(&tile, &addr);
rc = coresight_read(tile, addr, data);
break;
case MEM_AP_REG_DRW:
case ADIV5_MEM_AP_REG_DRW:
addr = (ap_tar & ~0x3) + ap_tar_inc;
ap_addr_2_tile(&tile, &addr);
rc = coresight_read(tile, addr, data);
@ -344,25 +344,25 @@ static int rshim_ap_q_write(struct adiv5_ap *ap, unsigned int reg,
}
switch (reg) {
case MEM_AP_REG_CSW:
case ADIV5_MEM_AP_REG_CSW:
ap_csw = data;
break;
case MEM_AP_REG_TAR:
case ADIV5_MEM_AP_REG_TAR:
ap_tar = data;
ap_tar_inc = 0;
break;
case MEM_AP_REG_BD0:
case MEM_AP_REG_BD1:
case MEM_AP_REG_BD2:
case MEM_AP_REG_BD3:
case ADIV5_MEM_AP_REG_BD0:
case ADIV5_MEM_AP_REG_BD1:
case ADIV5_MEM_AP_REG_BD2:
case ADIV5_MEM_AP_REG_BD3:
addr = (ap_tar & ~0xf) + (reg & 0x0C);
ap_addr_2_tile(&tile, &addr);
rc = coresight_write(tile, addr, data);
break;
case MEM_AP_REG_DRW:
case ADIV5_MEM_AP_REG_DRW:
ap_drw = data;
addr = (ap_tar & ~0x3) + ap_tar_inc;
ap_addr_2_tile(&tile, &addr);

26
src/jtag/drivers/stlink_usb.c
View File

@ -4286,7 +4286,7 @@ static int stlink_dap_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *d
uint32_t dummy;
int retval;
if (reg != AP_REG_IDR) {
if (reg != ADIV5_AP_REG_IDR) {
retval = stlink_dap_open_ap(ap->ap_num);
if (retval != ERROR_OK)
return retval;
@ -4591,7 +4591,7 @@ static void stlink_dap_run_internal(struct adiv5_dap *dap)
break;
case CMD_AP_WRITE:
/* ignore increment packed, not supported */
if (q->ap_w.reg == MEM_AP_REG_CSW)
if (q->ap_w.reg == ADIV5_MEM_AP_REG_CSW)
q->ap_w.data &= ~CSW_ADDRINC_PACKED;
retval = stlink_dap_ap_write(q->ap_w.ap, q->ap_w.reg, q->ap_w.data);
break;
@ -4736,18 +4736,18 @@ static int stlink_dap_op_queue_ap_read(struct adiv5_ap *ap, unsigned int reg,
/* test STLINK_F_HAS_CSW implicitly tests STLINK_F_HAS_MEM_16BIT, STLINK_F_HAS_MEM_RD_NO_INC
* and STLINK_F_HAS_RW_MISC */
if ((stlink_dap_handle->version.flags & STLINK_F_HAS_CSW) &&
(reg == MEM_AP_REG_DRW || reg == MEM_AP_REG_BD0 || reg == MEM_AP_REG_BD1 ||
reg == MEM_AP_REG_BD2 || reg == MEM_AP_REG_BD3)) {
(reg == ADIV5_MEM_AP_REG_DRW || reg == ADIV5_MEM_AP_REG_BD0 || reg == ADIV5_MEM_AP_REG_BD1 ||
reg == ADIV5_MEM_AP_REG_BD2 || reg == ADIV5_MEM_AP_REG_BD3)) {
/* de-queue previous write-TAR */
struct dap_queue *prev_q = q - 1;
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == MEM_AP_REG_TAR) {
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == ADIV5_MEM_AP_REG_TAR) {
stlink_dap_handle->queue_index = i;
i--;
q = prev_q;
prev_q--;
}
/* de-queue previous write-CSW if it didn't changed ap->csw_default */
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == MEM_AP_REG_CSW &&
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == ADIV5_MEM_AP_REG_CSW &&
!prev_q->ap_w.changes_csw_default) {
stlink_dap_handle->queue_index = i;
q = prev_q;
@ -4769,7 +4769,7 @@ static int stlink_dap_op_queue_ap_read(struct adiv5_ap *ap, unsigned int reg,
return ERROR_FAIL;
}
q->mem_ap.addr = (reg == MEM_AP_REG_DRW) ? ap->tar_value : ((ap->tar_value & ~0x0f) | (reg & 0x0c));
q->mem_ap.addr = (reg == ADIV5_MEM_AP_REG_DRW) ? ap->tar_value : ((ap->tar_value & ~0x0f) | (reg & 0x0c));
q->mem_ap.ap = ap;
q->mem_ap.p_data = data;
q->mem_ap.csw = ap->csw_default;
@ -4802,18 +4802,18 @@ static int stlink_dap_op_queue_ap_write(struct adiv5_ap *ap, unsigned int reg,
/* test STLINK_F_HAS_CSW implicitly tests STLINK_F_HAS_MEM_16BIT, STLINK_F_HAS_MEM_WR_NO_INC
* and STLINK_F_HAS_RW_MISC */
if ((stlink_dap_handle->version.flags & STLINK_F_HAS_CSW) &&
(reg == MEM_AP_REG_DRW || reg == MEM_AP_REG_BD0 || reg == MEM_AP_REG_BD1 ||
reg == MEM_AP_REG_BD2 || reg == MEM_AP_REG_BD3)) {
(reg == ADIV5_MEM_AP_REG_DRW || reg == ADIV5_MEM_AP_REG_BD0 || reg == ADIV5_MEM_AP_REG_BD1 ||
reg == ADIV5_MEM_AP_REG_BD2 || reg == ADIV5_MEM_AP_REG_BD3)) {
/* de-queue previous write-TAR */
struct dap_queue *prev_q = q - 1;
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == MEM_AP_REG_TAR) {
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == ADIV5_MEM_AP_REG_TAR) {
stlink_dap_handle->queue_index = i;
i--;
q = prev_q;
prev_q--;
}
/* de-queue previous write-CSW if it didn't changed ap->csw_default */
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == MEM_AP_REG_CSW &&
if (i && prev_q->cmd == CMD_AP_WRITE && prev_q->ap_w.ap == ap && prev_q->ap_w.reg == ADIV5_MEM_AP_REG_CSW &&
!prev_q->ap_w.changes_csw_default) {
stlink_dap_handle->queue_index = i;
q = prev_q;
@ -4835,7 +4835,7 @@ static int stlink_dap_op_queue_ap_write(struct adiv5_ap *ap, unsigned int reg,
return ERROR_FAIL;
}
q->mem_ap.addr = (reg == MEM_AP_REG_DRW) ? ap->tar_value : ((ap->tar_value & ~0x0f) | (reg & 0x0c));
q->mem_ap.addr = (reg == ADIV5_MEM_AP_REG_DRW) ? ap->tar_value : ((ap->tar_value & ~0x0f) | (reg & 0x0c));
q->mem_ap.ap = ap;
q->mem_ap.data = data;
q->mem_ap.csw = ap->csw_default;
@ -4848,7 +4848,7 @@ static int stlink_dap_op_queue_ap_write(struct adiv5_ap *ap, unsigned int reg,
q->ap_w.reg = reg;
q->ap_w.ap = ap;
q->ap_w.data = data;
if (reg == MEM_AP_REG_CSW && ap->csw_default != last_csw_default[ap->ap_num]) {
if (reg == ADIV5_MEM_AP_REG_CSW && ap->csw_default != last_csw_default[ap->ap_num]) {
q->ap_w.changes_csw_default = true;
last_csw_default[ap->ap_num] = ap->csw_default;
} else {

81
src/target/adi_v5_jtag.c
View File

@ -10,6 +10,8 @@
*
* Copyright (C) 2009-2010 by David Brownell
*
* Copyright (C) 2020-2021, Ampere Computing LLC *
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -55,7 +57,7 @@
static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
#ifdef DEBUG_WAIT
static const char *dap_reg_name(int instr, int reg_addr)
static const char *dap_reg_name(struct adiv5_dap *dap, uint8_t instr, uint16_t reg_addr)
{
char *reg_name = "UNK";
@ -83,41 +85,32 @@ static const char *dap_reg_name(int instr, int reg_addr)
}
if (instr == JTAG_DP_APACC) {
switch (reg_addr) {
case MEM_AP_REG_CSW:
if (reg_addr == MEM_AP_REG_CSW(dap))
reg_name = "CSW";
break;
case MEM_AP_REG_TAR:
else if (reg_addr == MEM_AP_REG_TAR(dap))
reg_name = "TAR";
break;
case MEM_AP_REG_DRW:
else if (reg_addr == MEM_AP_REG_TAR64(dap))
reg_name = "TAR64";
else if (reg_addr == MEM_AP_REG_DRW(dap))
reg_name = "DRW";
break;
case MEM_AP_REG_BD0:
else if (reg_addr == MEM_AP_REG_BD0(dap))
reg_name = "BD0";
break;
case MEM_AP_REG_BD1:
else if (reg_addr == MEM_AP_REG_BD1(dap))
reg_name = "BD1";
break;
case MEM_AP_REG_BD2:
else if (reg_addr == MEM_AP_REG_BD2(dap))
reg_name = "BD2";
break;
case MEM_AP_REG_BD3:
else if (reg_addr == MEM_AP_REG_BD3(dap))
reg_name = "BD3";
break;
case MEM_AP_REG_CFG:
else if (reg_addr == MEM_AP_REG_CFG(dap))
reg_name = "CFG";
break;
case MEM_AP_REG_BASE:
else if (reg_addr == MEM_AP_REG_BASE(dap))
reg_name = "BASE";
break;
case AP_REG_IDR:
else if (reg_addr == MEM_AP_REG_BASE64(dap))
reg_name = "BASE64";
else if (reg_addr == AP_REG_IDR(dap))
reg_name = "IDR";
break;
default:
else
reg_name = "UNK";
break;
}
}
return reg_name;
@ -127,7 +120,7 @@ static const char *dap_reg_name(int instr, int reg_addr)
struct dap_cmd {
struct list_head lh;
uint8_t instr;
uint8_t reg_addr;
uint16_t reg_addr;
uint8_t rnw;
uint8_t *invalue;
uint8_t ack;
@ -147,12 +140,12 @@ struct dap_cmd_pool {
struct dap_cmd cmd;
};
static void log_dap_cmd(const char *header, struct dap_cmd *el)
static void log_dap_cmd(struct adiv5_dap *dap, const char *header, struct dap_cmd *el)
{
#ifdef DEBUG_WAIT
LOG_DEBUG("%s: %2s %6s %5s 0x%08x 0x%08x %2s", header,
el->instr == JTAG_DP_APACC ? "AP" : "DP",
dap_reg_name(el->instr, el->reg_addr),
dap_reg_name(dap, el->instr, el->reg_addr),
el->rnw == DPAP_READ ? "READ" : "WRITE",
buf_get_u32(el->outvalue_buf, 0, 32),
buf_get_u32(el->invalue, 0, 32),
@ -170,7 +163,7 @@ static int jtag_limit_queue_size(struct adiv5_dap *dap)
}
static struct dap_cmd *dap_cmd_new(struct adiv5_dap *dap, uint8_t instr,
uint8_t reg_addr, uint8_t rnw,
uint16_t reg_addr, uint8_t rnw,
uint8_t *outvalue, uint8_t *invalue,
uint32_t memaccess_tck)
{
@ -274,9 +267,9 @@ static int adi_jtag_dp_scan_cmd(struct adiv5_dap *dap, struct dap_cmd *cmd, uint
* See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
*/
if (cmd->instr == JTAG_DP_APACC) {
if (((cmd->reg_addr == MEM_AP_REG_DRW)
|| ((cmd->reg_addr & 0xF0) == MEM_AP_REG_BD0))
&& (cmd->memaccess_tck != 0))
if ((cmd->reg_addr == MEM_AP_REG_DRW(dap) ||
(cmd->reg_addr & 0xFF0) == MEM_AP_REG_BD0(dap)) &&
cmd->memaccess_tck != 0)
jtag_add_runtest(cmd->memaccess_tck, TAP_IDLE);
}
@ -315,7 +308,7 @@ static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd,
*/
static int adi_jtag_dp_scan(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t rnw,
uint8_t instr, uint16_t reg_addr, uint8_t rnw,
uint8_t *outvalue, uint8_t *invalue,
uint32_t memaccess_tck, uint8_t *ack)
{
@ -377,7 +370,7 @@ static int adi_jtag_finish_read(struct adiv5_dap *dap)
}
static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t rnw,
uint8_t instr, uint16_t reg_addr, uint8_t rnw,
uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck)
{
int retval;
@ -417,13 +410,13 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
/* skip all completed transactions up to the first WAIT */
list_for_each_entry(el, &dap->cmd_journal, lh) {
if (el->ack == JTAG_ACK_OK_FAULT) {
log_dap_cmd("LOG", el);
log_dap_cmd(dap, "LOG", el);
} else if (el->ack == JTAG_ACK_WAIT) {
found_wait = 1;
break;
} else {
LOG_ERROR("Invalid ACK (%1x) in DAP response", el->ack);
log_dap_cmd("ERR", el);
log_dap_cmd(dap, "ERR", el);
retval = ERROR_JTAG_DEVICE_ERROR;
goto done;
}
@ -436,14 +429,14 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
if (found_wait && el != list_first_entry(&dap->cmd_journal, struct dap_cmd, lh)) {
prev = list_entry(el->lh.prev, struct dap_cmd, lh);
if (prev->rnw == DPAP_READ) {
log_dap_cmd("PND", prev);
log_dap_cmd(dap, "PND", prev);
/* search for the next OK transaction, it contains
* the result of the previous READ */
tmp = el;
list_for_each_entry_from(tmp, &dap->cmd_journal, lh) {
if (tmp->ack == JTAG_ACK_OK_FAULT) {
/* recover the read value */
log_dap_cmd("FND", tmp);
log_dap_cmd(dap, "FND", tmp);
if (el->invalue != el->invalue_buf) {
uint32_t invalue = le_to_h_u32(tmp->invalue);
memcpy(el->invalue, &invalue, sizeof(uint32_t));
@ -454,7 +447,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
}
if (prev) {
log_dap_cmd("LST", el);
log_dap_cmd(dap, "LST", el);
/*
* At this point we're sure that no previous
@ -477,7 +470,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
if (retval != ERROR_OK)
break;
if (tmp->ack == JTAG_ACK_OK_FAULT) {
log_dap_cmd("FND", tmp);
log_dap_cmd(dap, "FND", tmp);
if (el->invalue != el->invalue_buf) {
uint32_t invalue = le_to_h_u32(tmp->invalue);
memcpy(el->invalue, &invalue, sizeof(uint32_t));
@ -486,7 +479,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
}
if (tmp->ack != JTAG_ACK_WAIT) {
LOG_ERROR("Invalid ACK (%1x) in DAP response", tmp->ack);
log_dap_cmd("ERR", tmp);
log_dap_cmd(dap, "ERR", tmp);
retval = ERROR_JTAG_DEVICE_ERROR;
break;
}
@ -523,7 +516,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
/* move all remaining transactions over to the replay list */
list_for_each_entry_safe_from(el, tmp, &dap->cmd_journal, lh) {
log_dap_cmd("REP", el);
log_dap_cmd(dap, "REP", el);
list_move_tail(&el->lh, &replay_list);
}
@ -560,7 +553,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
retval = adi_jtag_dp_scan_cmd_sync(dap, el, NULL);
if (retval != ERROR_OK)
break;
log_dap_cmd("REC", el);
log_dap_cmd(dap, "REC", el);
if (el->ack == JTAG_ACK_OK_FAULT) {
if (el->invalue != el->invalue_buf) {
uint32_t invalue = le_to_h_u32(el->invalue);
@ -570,7 +563,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
}
if (el->ack != JTAG_ACK_WAIT) {
LOG_ERROR("Invalid ACK (%1x) in DAP response", el->ack);
log_dap_cmd("ERR", el);
log_dap_cmd(dap, "ERR", el);
retval = ERROR_JTAG_DEVICE_ERROR;
break;
}

54
src/target/arm_adi_v5.c
View File

@ -107,7 +107,7 @@ static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
if (csw != ap->csw_value) {
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW(ap->dap), csw);
if (retval != ERROR_OK) {
ap->csw_value = 0;
return retval;
@ -121,11 +121,11 @@ static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
{
if (!ap->tar_valid || tar != ap->tar_value) {
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, (uint32_t)(tar & 0xffffffffUL));
int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR(ap->dap), (uint32_t)(tar & 0xffffffffUL));
if (retval == ERROR_OK && is_64bit_ap(ap)) {
/* See if bits 63:32 of tar is different from last setting */
if ((ap->tar_value >> 32) != (tar >> 32))
retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64, (uint32_t)(tar >> 32));
retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64(ap->dap), (uint32_t)(tar >> 32));
}
if (retval != ERROR_OK) {
ap->tar_valid = false;
@ -142,9 +142,9 @@ static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
uint32_t lower;
uint32_t upper = 0;
int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, &lower);
int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR(ap->dap), &lower);
if (retval == ERROR_OK && is_64bit_ap(ap))
retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64, &upper);
retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64(ap->dap), &upper);
if (retval != ERROR_OK) {
ap->tar_valid = false;
@ -252,7 +252,7 @@ int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
if (retval != ERROR_OK)
return retval;
return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
return dap_queue_ap_read(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC), value);
}
/**
@ -304,7 +304,7 @@ int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
if (retval != ERROR_OK)
return retval;
return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
return dap_queue_ap_write(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC),
value);
}
@ -436,7 +436,7 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz
nbytes -= this_size;
retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW(dap), outvalue);
if (retval != ERROR_OK)
break;
@ -533,7 +533,7 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint
if (retval != ERROR_OK)
break;
retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW(dap), read_ptr++);
if (retval != ERROR_OK)
break;
@ -780,7 +780,7 @@ int mem_ap_init(struct adiv5_ap *ap)
/* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
/* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &cfg);
if (retval != ERROR_OK)
return retval;
@ -795,7 +795,7 @@ int mem_ap_init(struct adiv5_ap *ap)
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW(dap), &csw);
if (retval != ERROR_OK)
return retval;
@ -983,7 +983,7 @@ int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adi
/* read the IDR register of the Access Port */
uint32_t id_val = 0;
int retval = dap_queue_ap_read(ap, AP_REG_IDR, &id_val);
int retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), &id_val);
if (retval != ERROR_OK) {
dap_put_ap(ap);
return retval;
@ -1074,19 +1074,19 @@ static int dap_get_debugbase(struct adiv5_ap *ap,
uint32_t baseptr_upper, baseptr_lower;
if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &ap->cfg_reg);
if (retval != ERROR_OK)
return retval;
}
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower);
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE(dap), &baseptr_lower);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), apid);
if (retval != ERROR_OK)
return retval;
/* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64(dap), &baseptr_upper);
if (retval != ERROR_OK)
return retval;
}
@ -2230,14 +2230,14 @@ COMMAND_HANDLER(dap_baseaddr_command)
return ERROR_FAIL;
}
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower);
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE(dap), &baseaddr_lower);
if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &ap->cfg_reg);
if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
/* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper);
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64(dap), &baseaddr_upper);
}
if (retval == ERROR_OK)
@ -2400,7 +2400,7 @@ COMMAND_HANDLER(dap_apid_command)
command_print(CMD, "Cannot get AP");
return ERROR_FAIL;
}
retval = dap_queue_ap_read(ap, AP_REG_IDR, &apid);
retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), &apid);
if (retval != ERROR_OK) {
dap_put_ap(ap);
return retval;
@ -2445,14 +2445,13 @@ COMMAND_HANDLER(dap_apreg_command)
if (CMD_ARGC == 3) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
switch (reg) {
case MEM_AP_REG_CSW:
/* see if user supplied register address is a match for the CSW or TAR register */
if (reg == MEM_AP_REG_CSW(dap)) {
ap->csw_value = 0; /* invalid, in case write fails */
retval = dap_queue_ap_write(ap, reg, value);
if (retval == ERROR_OK)
ap->csw_value = value;
break;
case MEM_AP_REG_TAR:
} else if (reg == MEM_AP_REG_TAR(dap)) {
retval = dap_queue_ap_write(ap, reg, value);
if (retval == ERROR_OK)
ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value;
@ -2463,8 +2462,7 @@ COMMAND_HANDLER(dap_apreg_command)
/* if tar_valid is false. */
ap->tar_valid = false;
}
break;
case MEM_AP_REG_TAR64:
} else if (reg == MEM_AP_REG_TAR64(dap)) {
retval = dap_queue_ap_write(ap, reg, value);
if (retval == ERROR_OK)
ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32);
@ -2472,10 +2470,8 @@ COMMAND_HANDLER(dap_apreg_command)
/* See above comment for the MEM_AP_REG_TAR failed write case */
ap->tar_valid = false;
}
break;
default:
} else {
retval = dap_queue_ap_write(ap, reg, value);
break;
}
} else {
retval = dap_queue_ap_read(ap, reg, &value);

65
src/target/arm_adi_v5.h
View File

@ -5,6 +5,8 @@
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2019-2021, Ampere Computing LLC *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@ -53,11 +55,15 @@
*/
#define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
#define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
#define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */
#define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */
#define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */
#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
#define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
#define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
#define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
#define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
#define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */
#define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
#define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
#define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
@ -76,6 +82,10 @@
#define WDERRCLR (1UL << 3) /* SWD-only */
#define ORUNERRCLR (1UL << 4) /* SWD-only */
/* Fields of register DP_DPIDR1 */
#define DP_DPIDR1_ASIZE_MASK (0x7F)
#define DP_DPIDR1_ERRMODE BIT(7)
/* Fields of the DP's CTRL/STAT register */
#define CORUNDETECT (1UL << 0)
#define SSTICKYORUN (1UL << 1)
@ -110,20 +120,49 @@
/* MEM-AP register addresses */
#define MEM_AP_REG_CSW 0x00
#define MEM_AP_REG_TAR 0x04
#define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
#define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
#define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
#define MEM_AP_REG_BD1 0x14
#define MEM_AP_REG_BD2 0x18
#define MEM_AP_REG_BD3 0x1C
#define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
#define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
#define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
#define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
#define ADIV5_MEM_AP_REG_CSW (0x00)
#define ADIV5_MEM_AP_REG_TAR (0x04)
#define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */
#define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */
#define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */
#define ADIV5_MEM_AP_REG_BD1 (0x14)
#define ADIV5_MEM_AP_REG_BD2 (0x18)
#define ADIV5_MEM_AP_REG_BD3 (0x1C)
#define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */
#define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */
#define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */
#define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */
#define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)
#define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)
#define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)
#define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)
#define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)
#define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)
#define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)
#define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)
#define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)
#define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)
#define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)
#define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)
#define MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)
#define MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)
#define MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)
#define MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)
#define MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)
#define MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)
#define MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)
#define MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)
#define MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)
#define MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)
#define MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)
#define MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)
/* Generic AP register address */
#define AP_REG_IDR 0xFC /* RO: Identification Register */
#define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */
#define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)
#define AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)
/* Fields of the MEM-AP's CSW register */
#define CSW_SIZE_MASK 7