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bluenrg: add support for bluenrg-lps device and board 

Added bluenrg-lps support
Added file for the board steval-idb012v1
Fixed size_info information using a mask
Changed the if condition in bluenrg-x.cfg to be valid only for bluenrg-1 and bluenrg-2

Signed-off-by: Salvatore Giorgio PECORINO <salvatore-giorgio.pecorino@st.com>
Change-Id: Ic0777ec0811ee6fac7d5e1d065c4629e47d84a1f
Reviewed-on: https://review.openocd.org/c/openocd/+/6928
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Salvatore Giorgio PECORINO 2022-04-12 18:15:42 +02:00 committed by Antonio Borneo
parent f88a7dde6a
commit ad5ca263e9
4 changed files with 27 additions and 6 deletions
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2
doc/openocd.texi
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@ -6418,7 +6418,7 @@ The AVR 8-bit microcontrollers from Atmel integrate flash memory.
@end deffn
@deffn {Flash Driver} {bluenrg-x}
STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
The driver automatically recognizes these chips using
the chip identification registers, and autoconfigures itself.

19
src/flash/nor/bluenrg-x.c
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@ -35,6 +35,8 @@
#define JTAG_IDCODE_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->jtag_idcode_reg)
#define FLASH_PAGE_SIZE(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_page_size)
#define FLASH_SIZE_REG_MASK (0xFFFF)
struct flash_ctrl_priv_data {
uint32_t die_id_reg;
uint32_t jtag_idcode_reg;
@ -75,6 +77,16 @@ static const struct flash_ctrl_priv_data flash_priv_data_lp = {
.part_name = "BLUENRG-LP",
};
static const struct flash_ctrl_priv_data flash_priv_data_lps = {
.die_id_reg = 0x40000000,
.jtag_idcode_reg = 0x40000004,
.flash_base = 0x10040000,
.flash_regs_base = 0x40001000,
.flash_page_size = 2048,
.jtag_idcode = 0x02028041,
.part_name = "BLUENRG-LPS",
};
struct bluenrgx_flash_bank {
bool probed;
uint32_t die_id;
@ -84,8 +96,8 @@ struct bluenrgx_flash_bank {
static const struct flash_ctrl_priv_data *flash_ctrl[] = {
&flash_priv_data_1,
&flash_priv_data_2,
&flash_priv_data_lp
};
&flash_priv_data_lp,
&flash_priv_data_lps};
/* flash_bank bluenrg-x 0 0 0 0 <target#> */
FLASH_BANK_COMMAND_HANDLER(bluenrgx_flash_bank_command)
@ -377,7 +389,7 @@ static int bluenrgx_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
if (idcode != flash_priv_data_lp.jtag_idcode) {
if ((idcode != flash_priv_data_lp.jtag_idcode) && (idcode != flash_priv_data_lps.jtag_idcode)) {
retval = target_read_u32(bank->target, BLUENRG2_JTAG_REG, &idcode);
if (retval != ERROR_OK)
return retval;
@ -395,6 +407,7 @@ static int bluenrgx_probe(struct flash_bank *bank)
}
}
retval = bluenrgx_read_flash_reg(bank, FLASH_SIZE_REG, &size_info);
size_info = size_info & FLASH_SIZE_REG_MASK;
if (retval != ERROR_OK)
return retval;

5
tcl/board/steval-idb012v1.cfg Normal file
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@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later.
# This is an evaluation board with a single BlueNRG-LPS chip.
set CHIPNAME bluenrg-lps
source [find interface/cmsis-dap.cfg]
source [find target/bluenrg-x.cfg]

7
tcl/target/bluenrg-x.cfg
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@ -47,11 +47,14 @@ if {![using_hla]} {
cortex_m reset_config sysresetreq
}
set JTAG_IDCODE_B2 0x0200A041
set JTAG_IDCODE_B1 0x0
$_TARGETNAME configure -event halted {
global WDOG_VALUE
global WDOG_VALUE_SET
set _JTAG_IDCODE [mrw 0x40000004]
if {$_JTAG_IDCODE != 0x0201E041} {
if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
# Stop watchdog during halt, if enabled. Only Bluenrg-1/2
set WDOG_VALUE [mrw 0x40700008]
if [expr {$WDOG_VALUE & (1 << 1)}] {
@ -64,7 +67,7 @@ $_TARGETNAME configure -event resumed {
global WDOG_VALUE
global WDOG_VALUE_SET
set _JTAG_IDCODE [mrw 0x40000004]
if {$_JTAG_IDCODE != 0x0201E041} {
if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
if {$WDOG_VALUE_SET} {
# Restore watchdog enable value after resume. Only Bluenrg-1/2
mww 0x40700008 $WDOG_VALUE